Searched refs:SPD_SDRAM_TCLK2_PULSE (Results 1 – 11 of 11) sorted by relevance
37 #define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency macro
45 #define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency macro
35 #define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency macro