| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/mm/nohash/ |
| H A D | 40x.c | 83 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */ in MMU_init_hw()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/mm/nohash/ |
| H A D | 40x.c | 83 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */ in MMU_init_hw()
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| /dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/mm/nohash/ |
| H A D | 40x.c | 83 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */ in MMU_init_hw()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/powerpc/include/asm/ |
| H A D | processor.h | 286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ macro
|