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Searched refs:SRDS2_MAX_LANES (Results 1 – 25 of 329) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
68 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/mpc86xx/
H A Dmpc8610_serdes.c14 #define SRDS2_MAX_LANES 4 macro
24 static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
65 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c14 #define SRDS2_MAX_LANES 2 macro
25 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
82 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c14 #define SRDS2_MAX_LANES 2 macro
25 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
82 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c14 #define SRDS2_MAX_LANES 2 macro
25 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
82 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c14 #define SRDS2_MAX_LANES 2 macro
25 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
82 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/
H A Dp1010_serdes.c15 #define SRDS2_MAX_LANES 2 macro
26 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()

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