| /dports/devel/libunwind/libunwind-1.5.0/src/mips/ |
| H A D | getcontext.S | 57 SREG (1)
58 SREG (0)
59 SREG (2)
60 SREG (3)
61 SREG (4)
62 SREG (5)
63 SREG (6)
64 SREG (7)
65 SREG (8)
66 SREG (9)
[all …]
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/riscv/cpu/ |
| H A D | mtrap.S | 19 #define SREG sw macro
23 #define SREG sd macro
34 SREG x1, 1 * REGBYTES(sp)
35 SREG x2, 2 * REGBYTES(sp)
36 SREG x3, 3 * REGBYTES(sp)
37 SREG x4, 4 * REGBYTES(sp)
38 SREG x5, 5 * REGBYTES(sp)
39 SREG x6, 6 * REGBYTES(sp)
40 SREG x7, 7 * REGBYTES(sp)
41 SREG x8, 8 * REGBYTES(sp)
[all …]
|