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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
31 ; SSE: # %bb.0:
35 ; SSE-NEXT: retq
52 ; SSE: # %bb.0:
56 ; SSE-NEXT: retq
82 ; SSE-NEXT: retq
106 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
163 ; SSE-NEXT: retq
[all …]
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]
H A Dvec-strict-cmp-128.ll11 ; SSE-32: # %bb.0:
22 ; SSE-32-NEXT: retl
25 ; SSE-64: # %bb.0:
30 ; SSE-64-NEXT: retq
76 ; SSE-32: # %bb.0:
117 ; SSE-32-NEXT: retl
154 ; SSE-64-NEXT: retq
242 ; SSE-32-NEXT: retl
279 ; SSE-64-NEXT: retq
367 ; SSE-32-NEXT: retl
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
31 ; SSE: # %bb.0:
35 ; SSE-NEXT: retq
52 ; SSE: # %bb.0:
56 ; SSE-NEXT: retq
82 ; SSE-NEXT: retq
106 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
163 ; SSE-NEXT: retq
[all …]
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]
H A Dvec-strict-cmp-128.ll11 ; SSE-32: # %bb.0:
22 ; SSE-32-NEXT: retl
25 ; SSE-64: # %bb.0:
30 ; SSE-64-NEXT: retq
76 ; SSE-32: # %bb.0:
117 ; SSE-32-NEXT: retl
154 ; SSE-64-NEXT: retq
242 ; SSE-32-NEXT: retl
279 ; SSE-64-NEXT: retq
367 ; SSE-32-NEXT: retl
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
31 ; SSE: # %bb.0:
35 ; SSE-NEXT: retq
52 ; SSE: # %bb.0:
56 ; SSE-NEXT: retq
82 ; SSE-NEXT: retq
106 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
163 ; SSE-NEXT: retq
[all …]
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
H A Dfp-intrinsics.ll25 ; X86-SSE-LABEL: f1:
38 ; SSE-LABEL: f1:
42 ; SSE-NEXT: retq
88 ; SSE-LABEL: f2:
145 ; SSE-LABEL: f3:
221 ; SSE-LABEL: f4:
276 ; SSE-LABEL: f5:
323 ; SSE-LABEL: f6:
379 ; SSE-LABEL: f7:
433 ; SSE-LABEL: f8:
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dmachine-combiner-int-vec.ll10 ; SSE: # %bb.0:
14 ; SSE-NEXT: retq
37 ; SSE: # %bb.0:
41 ; SSE-NEXT: retq
64 ; SSE: # %bb.0:
68 ; SSE-NEXT: retq
100 ; SSE-NEXT: retq
130 ; SSE-NEXT: retq
160 ; SSE-NEXT: retq
199 ; SSE-NEXT: retq
[all …]
/dports/devel/vc/Vc-1.4.2/Vc/sse/
H A Dvector.tcc59 Vc_INTRINSIC SSE:: uint_m operator> (SSE:: uint_v a, SSE:: uint_v b) { in operator >()
67 Vc_INTRINSIC SSE::ushort_m operator> (SSE::ushort_v a, SSE::ushort_v b) { in operator >()
78 Vc_INTRINSIC SSE:: uint_m operator< (SSE:: uint_v a, SSE:: uint_v b) { in operator <()
86 Vc_INTRINSIC SSE::ushort_m operator< (SSE::ushort_v a, SSE::ushort_v b) { in operator <()
110 Vc_INTRINSIC SSE::Vector<T> operator^(SSE::Vector<T> a, SSE::Vector<T> b) in operator ^()
115 Vc_INTRINSIC SSE::Vector<T> operator&(SSE::Vector<T> a, SSE::Vector<T> b) in operator &()
120 Vc_INTRINSIC SSE::Vector<T> operator|(SSE::Vector<T> a, SSE::Vector<T> b) in operator |()
126 Vc_INTRINSIC SSE::Vector<T> operator+(SSE::Vector<T> a, SSE::Vector<T> b) in operator +()
131 Vc_INTRINSIC SSE::Vector<T> operator-(SSE::Vector<T> a, SSE::Vector<T> b) in operator -()
136 Vc_INTRINSIC SSE::Vector<T> operator*(SSE::Vector<T> a, SSE::Vector<T> b) in operator *()
[all …]
H A Dlimits.h52 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::short_v min() Vc_NOEXCEPT { return ::Vc::SSE::se…
64 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::uint_v min() Vc_NOEXCEPT { return ::Vc::SSE::uin…
66 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::uint_v epsilon() Vc_NOEXCEPT { return ::Vc::SSE::uin…
67 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::uint_v round_error() Vc_NOEXCEPT { return ::Vc::SSE::uin…
76 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::int_v min() Vc_NOEXCEPT { return ::Vc::SSE::setm…
78 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::int_v epsilon() Vc_NOEXCEPT { return ::Vc::SSE::int_…
79 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::int_v round_error() Vc_NOEXCEPT { return ::Vc::SSE::int_…
80 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::int_v infinity() Vc_NOEXCEPT { return ::Vc::SSE::int_…
81 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::int_v quiet_NaN() Vc_NOEXCEPT { return ::Vc::SSE::int_…
82 …static Vc_INTRINSIC Vc_CONST ::Vc::SSE::int_v signaling_NaN() Vc_NOEXCEPT { return ::Vc::SSE::int_…
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/
H A Dwiden_bitops-0.ll11 ; X32-SSE: # %bb.0:
14 ; X32-SSE-NEXT: retl
17 ; X64-SSE: # %bb.0:
20 ; X64-SSE-NEXT: retq
30 ; X32-SSE: # %bb.0:
33 ; X32-SSE-NEXT: retl
39 ; X64-SSE-NEXT: retq
52 ; X32-SSE-NEXT: retl
58 ; X64-SSE-NEXT: retq
75 ; X32-SSE-NEXT: retl
[all …]

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