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Searched refs:STATE_DDR (Results 1 – 25 of 82) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/target/xtensa/core-sample_controller/
H A Dxtensa-modules.inc.c163 STATE_DDR, enumerator
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/xtensa/core-sample_controller/
H A Dxtensa-modules.inc.c163 STATE_DDR, enumerator
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/xtensa/core-sample_controller/
H A Dxtensa-modules.inc.c163 STATE_DDR, enumerator
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/emulators/qemu42/qemu-4.2.1/target/xtensa/core-sample_controller/
H A Dxtensa-modules.inc.c163 STATE_DDR, enumerator
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/xtensa/core-sample_controller/
H A Dxtensa-modules.inc.c163 STATE_DDR, enumerator
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/bfd/
H A Dxtensa-modules.c145 #define STATE_DDR 3 macro
3633 { { STATE_DDR }, 'i' }
3642 { { STATE_DDR }, 'o' }
3651 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-utils/qemu-4.2.1/target/xtensa/core-fsf/
H A Dxtensa-modules.inc.c156 #define STATE_DDR 3 macro
3855 { { STATE_DDR }, 'i' }
3866 { { STATE_DDR }, 'o' }
3877 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/xtensa/core-fsf/
H A Dxtensa-modules.inc.c156 #define STATE_DDR 3 macro
3855 { { STATE_DDR }, 'i' }
3866 { { STATE_DDR }, 'o' }
3877 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/xtensa/core-fsf/
H A Dxtensa-modules.inc.c156 #define STATE_DDR 3 macro
3855 { { STATE_DDR }, 'i' }
3866 { { STATE_DDR }, 'o' }
3877 { { STATE_DDR }, 'm' }
/dports/emulators/qemu42/qemu-4.2.1/target/xtensa/core-fsf/
H A Dxtensa-modules.inc.c156 #define STATE_DDR 3 macro
3855 { { STATE_DDR }, 'i' }
3866 { { STATE_DDR }, 'o' }
3877 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/xtensa/core-fsf/
H A Dxtensa-modules.inc.c156 #define STATE_DDR 3 macro
3855 { { STATE_DDR }, 'i' }
3866 { { STATE_DDR }, 'o' }
3877 { { STATE_DDR }, 'm' }
/dports/devel/djgpp-binutils/binutils-2.17/bfd/
H A Dxtensa-modules.c156 #define STATE_DDR 3 macro
3871 { { STATE_DDR }, 'i' }
3882 { { STATE_DDR }, 'o' }
3893 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-utils/qemu-4.2.1/target/xtensa/core-de212/
H A Dxtensa-modules.inc.c178 STATE_DDR, enumerator
4962 { { STATE_DDR }, 'i' }
4971 { { STATE_DDR }, 'o' }
4980 { { STATE_DDR }, 'm' }
4990 { { STATE_DDR }, 'o' }
4999 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/xtensa/core-de212/
H A Dxtensa-modules.inc.c178 STATE_DDR, enumerator
4962 { { STATE_DDR }, 'i' }
4971 { { STATE_DDR }, 'o' }
4980 { { STATE_DDR }, 'm' }
4990 { { STATE_DDR }, 'o' }
4999 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/xtensa/core-de212/
H A Dxtensa-modules.inc.c178 STATE_DDR, enumerator
4962 { { STATE_DDR }, 'i' }
4971 { { STATE_DDR }, 'o' }
4980 { { STATE_DDR }, 'm' }
4990 { { STATE_DDR }, 'o' }
4999 { { STATE_DDR }, 'i' }
/dports/emulators/qemu42/qemu-4.2.1/target/xtensa/core-de212/
H A Dxtensa-modules.inc.c178 STATE_DDR, enumerator
4962 { { STATE_DDR }, 'i' }
4971 { { STATE_DDR }, 'o' }
4980 { { STATE_DDR }, 'm' }
4990 { { STATE_DDR }, 'o' }
4999 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/xtensa/core-de212/
H A Dxtensa-modules.inc.c178 STATE_DDR, enumerator
4962 { { STATE_DDR }, 'i' }
4971 { { STATE_DDR }, 'o' }
4980 { { STATE_DDR }, 'm' }
4990 { { STATE_DDR }, 'o' }
4999 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-utils/qemu-4.2.1/target/xtensa/core-dc232b/
H A Dxtensa-modules.inc.c192 #define STATE_DDR 3 macro
4976 { { STATE_DDR }, 'i' }
4987 { { STATE_DDR }, 'o' }
4998 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/xtensa/core-dc232b/
H A Dxtensa-modules.inc.c192 #define STATE_DDR 3 macro
4976 { { STATE_DDR }, 'i' }
4987 { { STATE_DDR }, 'o' }
4998 { { STATE_DDR }, 'm' }
/dports/emulators/qemu42/qemu-4.2.1/target/xtensa/core-dc232b/
H A Dxtensa-modules.inc.c192 #define STATE_DDR 3 macro
4976 { { STATE_DDR }, 'i' }
4987 { { STATE_DDR }, 'o' }
4998 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/xtensa/core-dc232b/
H A Dxtensa-modules.inc.c192 #define STATE_DDR 3 macro
4976 { { STATE_DDR }, 'i' }
4987 { { STATE_DDR }, 'o' }
4998 { { STATE_DDR }, 'm' }
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/xtensa/core-dc232b/
H A Dxtensa-modules.inc.c192 #define STATE_DDR 3 macro
4976 { { STATE_DDR }, 'i' }
4987 { { STATE_DDR }, 'o' }
4998 { { STATE_DDR }, 'm' }
/dports/emulators/qemu5/qemu-5.2.0/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc163 STATE_DDR,
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc163 STATE_DDR,
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }
/dports/emulators/qemu/qemu-6.2.0/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc163 STATE_DDR,
4271 { { STATE_DDR }, 'i' }
4280 { { STATE_DDR }, 'o' }
4289 { { STATE_DDR }, 'm' }
4299 { { STATE_DDR }, 'o' }
4308 { { STATE_DDR }, 'i' }

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