| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_interactive.c | 40 [STEP_DDR_RESET] = "DDR_RESET",
266 if (!stm32mp1_check_step(step, STEP_DDR_RESET)) in stm32mp1_do_param()
309 if (value != STEP_DDR_RESET && in stm32mp1_do_step()
391 if (next_step < 0 && step == STEP_DDR_RESET) { in stm32mp1_ddr_interactive()
395 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
401 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
444 next_step = STEP_DDR_RESET; in stm32mp1_ddr_interactive()
496 return next_step == STEP_DDR_RESET; in stm32mp1_ddr_interactive()
|