Home
last modified time | relevance | path

Searched refs:SUBREG (Results 1 – 25 of 4225) sorted by relevance

12345678910>>...169

/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/config/d30v/
H A Dd30v.h1939 { "gpr_operand", { REG, SUBREG }}, \
1940 { "accum_operand", { REG, SUBREG }}, \
1941 { "gpr_or_accum_operand", { REG, SUBREG }}, \
1942 { "cr_operand", { REG, SUBREG }}, \
1943 { "repeat_operand", { REG, SUBREG }}, \
1944 { "flag_operand", { REG, SUBREG }}, \
1945 { "br_flag_operand", { REG, SUBREG }}, \
1947 { "gpr_or_br_flag_operand", { REG, SUBREG }}, \
1948 { "f0_operand", { REG, SUBREG }}, \
1949 { "f1_operand", { REG, SUBREG }}, \
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/config/d30v/
H A Dd30v.h1939 { "gpr_operand", { REG, SUBREG }}, \
1940 { "accum_operand", { REG, SUBREG }}, \
1941 { "gpr_or_accum_operand", { REG, SUBREG }}, \
1942 { "cr_operand", { REG, SUBREG }}, \
1943 { "repeat_operand", { REG, SUBREG }}, \
1944 { "flag_operand", { REG, SUBREG }}, \
1945 { "br_flag_operand", { REG, SUBREG }}, \
1947 { "gpr_or_br_flag_operand", { REG, SUBREG }}, \
1948 { "f0_operand", { REG, SUBREG }}, \
1949 { "f1_operand", { REG, SUBREG }}, \
[all …]
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc48/gcc-4.8.5/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.c-torture/compile/
H A Dpr44784.c2 enum rtx_code { SUBREG }; enumerator
33 if (values[(reg->code == SUBREG in defs_to_varying()
36 ssa_edges->elms [(reg->code == SUBREG in defs_to_varying()
40 << (reg->code == SUBREG in defs_to_varying()
43 values[(reg->code == SUBREG in defs_to_varying()
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/config/frv/
H A Dfrv.h3062 { "fpr_operand", { REG, SUBREG }}, \
3063 { "even_reg_operand", { REG, SUBREG }}, \
3064 { "odd_reg_operand", { REG, SUBREG }}, \
3065 { "even_gpr_operand", { REG, SUBREG }}, \
3066 { "odd_gpr_operand", { REG, SUBREG }}, \
3067 { "quad_fpr_operand", { REG, SUBREG }}, \
3068 { "even_fpr_operand", { REG, SUBREG }}, \
3069 { "odd_fpr_operand", { REG, SUBREG }}, \
3100 { "acc_operand", { REG, SUBREG }}, \
3101 { "even_acc_operand", { REG, SUBREG }}, \
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/config/frv/
H A Dfrv.h3062 { "fpr_operand", { REG, SUBREG }}, \
3063 { "even_reg_operand", { REG, SUBREG }}, \
3064 { "odd_reg_operand", { REG, SUBREG }}, \
3065 { "even_gpr_operand", { REG, SUBREG }}, \
3066 { "odd_gpr_operand", { REG, SUBREG }}, \
3067 { "quad_fpr_operand", { REG, SUBREG }}, \
3068 { "even_fpr_operand", { REG, SUBREG }}, \
3069 { "odd_fpr_operand", { REG, SUBREG }}, \
3100 { "acc_operand", { REG, SUBREG }}, \
3101 { "even_acc_operand", { REG, SUBREG }}, \
[all …]

12345678910>>...169