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Searched refs:SUN4I_SPI0_CTL (Results 1 – 25 of 62) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08) macro
132 setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
146 clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
248 SUN4I_SPI0_CTL, in spi0_read_data()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08) macro
132 setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
146 clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
248 SUN4I_SPI0_CTL, in spi0_read_data()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08) macro
132 setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
146 clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
248 SUN4I_SPI0_CTL, in spi0_read_data()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08) macro
132 setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
146 clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
248 SUN4I_SPI0_CTL, in spi0_read_data()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08) macro
132 setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
146 clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
248 SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-sunxi/
H A Dspl_spi_sunxi.c44 #define SUN4I_SPI0_CTL 0x08 macro
173 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_enable_clock()
189 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | in spi0_disable_clock()
297 base + SUN4I_SPI0_CTL, in spi0_read_data()

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