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Searched refs:ShiftOperand (Results 1 – 25 of 45) sorted by relevance

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/dports/lang/v8/v8-9.6.180.12/src/execution/arm64/
H A Dsimulator-arm64.cc934 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { in ShiftOperand() function in v8::internal::Simulator
1668 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1671 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1710 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1714 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
2520 result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift); in DataProcessing2Source()
H A Dsimulator-arm64.h1538 T ShiftOperand(T value, Shift shift_type, unsigned amount);
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/execution/arm64/
H A Dsimulator-arm64.cc897 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { in ShiftOperand() function in v8::internal::Simulator
1632 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1635 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1674 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1678 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
2482 result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift); in DataProcessing2Source()
H A Dsimulator-arm64.h1519 T ShiftOperand(T value, Shift shift_type, unsigned amount);
/dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/execution/arm64/
H A Dsimulator-arm64.cc897 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { in ShiftOperand() function in v8::internal::Simulator
1632 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1635 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1674 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1678 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
2482 result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift); in DataProcessing2Source()
H A Dsimulator-arm64.h1519 T ShiftOperand(T value, Shift shift_type, unsigned amount);
/dports/www/node10/node-v10.24.1/deps/v8/src/arm64/
H A Dsimulator-arm64.cc831 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { in ShiftOperand() function in v8::internal::Simulator
1557 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1560 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1603 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1607 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
2377 result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift); in DataProcessing2Source()
H A Dsimulator-arm64.h1371 T ShiftOperand(T value,
/dports/www/firefox-esr/firefox-91.8.0/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp261 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() function in vixl::Simulator
867 int64_t op2 = ShiftOperand(reg_size, in VisitAddSubShifted()
914 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
1743 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, in VisitDataProcessing2Source()
H A DSimulator-vixl.h1180 int64_t ShiftOperand(unsigned reg_size,
/dports/www/firefox/firefox-99.0/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp261 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() function in vixl::Simulator
867 int64_t op2 = ShiftOperand(reg_size, in VisitAddSubShifted()
914 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
1743 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, in VisitDataProcessing2Source()
H A DSimulator-vixl.h1180 int64_t ShiftOperand(unsigned reg_size,
/dports/mail/thunderbird/thunderbird-91.8.0/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp261 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() function in vixl::Simulator
867 int64_t op2 = ShiftOperand(reg_size, in VisitAddSubShifted()
914 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
1743 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, in VisitDataProcessing2Source()
H A DSimulator-vixl.h1180 int64_t ShiftOperand(unsigned reg_size,
/dports/www/firefox-legacy/firefox-52.8.0esr/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp255 int64_t Simulator::ShiftOperand(unsigned reg_size,
861 int64_t op2 = ShiftOperand(reg_size,
908 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
1706 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op,
H A DSimulator-vixl.h1355 int64_t ShiftOperand(unsigned reg_size,
/dports/lang/spidermonkey60/firefox-60.9.0/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp255 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() function in vixl::Simulator
861 int64_t op2 = ShiftOperand(reg_size, in VisitAddSubShifted()
908 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
1737 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, in VisitDataProcessing2Source()
H A DSimulator-vixl.h1354 int64_t ShiftOperand(unsigned reg_size,
/dports/lang/spidermonkey78/firefox-78.9.0/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp261 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() function in vixl::Simulator
867 int64_t op2 = ShiftOperand(reg_size, in VisitAddSubShifted()
914 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
1743 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, in VisitDataProcessing2Source()
H A DSimulator-vixl.h1182 int64_t ShiftOperand(unsigned reg_size,
/dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/mozjs-45/extract/js/src/jit/arm64/vixl/
H A DSimulator-vixl.cpp272 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() function in vixl::Simulator
878 int64_t op2 = ShiftOperand(reg_size, in VisitAddSubShifted()
925 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
1723 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, in VisitDataProcessing2Source()
H A DSimulator-vixl.h1466 int64_t ShiftOperand(unsigned reg_size,
/dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/wasm/baseline/x64/
H A Dliftoff-assembler-x64.h2215 template <typename ShiftOperand>
2217 LiftoffRegister lhs, ShiftOperand rhs,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp8257 SDValue ShiftOperand = N->getOperand(0); in combineShiftToMULH() local
8258 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
8262 SDValue LeftOp = ShiftOperand.getOperand(0); in combineShiftToMULH()
8263 SDValue RightOp = ShiftOperand.getOperand(1); in combineShiftToMULH()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp8103 SDValue ShiftOperand = N->getOperand(0); in combineShiftToMULH() local
8104 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
8108 SDValue LeftOp = ShiftOperand.getOperand(0); in combineShiftToMULH()
8109 SDValue RightOp = ShiftOperand.getOperand(1); in combineShiftToMULH()

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