/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4657 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4673 Src0IsKill); in selectRem() 4721 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4724 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4735 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4742 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4936 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4939 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4966 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 432 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 452 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 464 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4663 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4679 Src0IsKill); in selectRem() 4727 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4730 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4741 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4748 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4942 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4945 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4972 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 451 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 463 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4664 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4680 Src0IsKill); in selectRem() 4728 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4731 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4742 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4749 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4943 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4946 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4973 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4657 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4673 Src0IsKill); in selectRem() 4721 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4724 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4735 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4742 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4936 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4939 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4966 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 432 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 452 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 464 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4663 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4679 Src0IsKill); in selectRem() 4727 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4730 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4741 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4748 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4942 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4945 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4972 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 451 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 463 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4664 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4680 Src0IsKill); in selectRem() 4728 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4731 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4742 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4749 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4943 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4946 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4973 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 451 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 463 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4664 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4680 Src0IsKill); in selectRem() 4728 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4731 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4742 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4749 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4943 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4946 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4973 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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H A D | AArch64FastISel.cpp | 4657 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local 4673 Src0IsKill); in selectRem() 4721 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local 4724 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul() 4735 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local 4742 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() 4936 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local 4939 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() 4966 Src0IsKill, AArch64CC::LT); in selectSDiv()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 451 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 463 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 432 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 452 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 464 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
H A D | AArch64SIMDInstrOpt.cpp | 432 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement() local 452 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 464 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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