| /dports/databases/mysql55-client/mysql-5.5.62/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 84 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
85 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
175 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
176 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
181 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
182 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/percona56-server/percona-server-5.6.51-91.0/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/percona56-client/percona-server-5.6.51-91.0/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/percona-pam-for-mysql/percona-server-5.6.51-91.0/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/xtrabackup/percona-xtrabackup-2.4.21/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/percona57-client/percona-server-5.7.36-39/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/mysqlwsrep57-server/mysql-wsrep-wsrep_5.7.35-25.27/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/percona57-pam-for-mysql/percona-server-5.7.36-39/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/percona57-server/percona-server-5.7.36-39/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/mysqlwsrep56-server/mysql-wsrep-wsrep_5.6.51-25.33/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/databases/mysql56-client/mysql-5.6.51/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 179 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
187 SrcReg2 = 0; in analyzeCompare()
193 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
207 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
212 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
213 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
285 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
305 if (SrcReg2 != 0) in optimizeCompareInstr()
331 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
383 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/databases/xtrabackup8/percona-xtrabackup-8.0.14/storage/ndb/include/kernel/ |
| H A D | Interpreter.hpp | 97 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
98 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
257 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
258 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
263 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
264 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = 0; in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = 0; in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int64_t &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int64_t ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, in optimizeCompareInstr() argument
305 if (SrcReg2 != 0) in optimizeCompareInstr()
331 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
383 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = 0; in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
|