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Searched refs:SubIdx1 (Results 1 – 16 of 16) sorted by relevance

/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2624 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
2631 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
2632 SubIdx1 = 0; in storeRegPairToStackSlot()
2636 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
2753 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
2761 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
2762 SubIdx1 = 0; in loadRegPairFromStackSlot()
2767 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2733 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
2740 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
2741 SubIdx1 = 0; in storeRegPairToStackSlot()
2745 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
2862 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
2870 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
2871 SubIdx1 = 0; in loadRegPairFromStackSlot()
2876 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2826 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
2833 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
2834 SubIdx1 = 0; in storeRegPairToStackSlot()
2838 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
2966 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
2974 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
2975 SubIdx1 = 0; in loadRegPairFromStackSlot()
2980 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2826 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
2833 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
2834 SubIdx1 = 0; in storeRegPairToStackSlot()
2838 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
2966 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
2974 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
2975 SubIdx1 = 0; in loadRegPairFromStackSlot()
2980 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2826 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
2833 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
2834 SubIdx1 = 0; in storeRegPairToStackSlot()
2838 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
2966 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
2974 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
2975 SubIdx1 = 0; in loadRegPairFromStackSlot()
2980 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3120 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3127 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3128 SubIdx1 = 0; in storeRegPairToStackSlot()
3132 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3272 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3280 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3281 SubIdx1 = 0; in loadRegPairFromStackSlot()
3286 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2991 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
2998 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
2999 SubIdx1 = 0; in storeRegPairToStackSlot()
3003 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3143 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3151 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3152 SubIdx1 = 0; in loadRegPairFromStackSlot()
3157 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3250 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3257 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3258 SubIdx1 = 0; in storeRegPairToStackSlot()
3262 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3402 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3410 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3411 SubIdx1 = 0; in loadRegPairFromStackSlot()
3416 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3020 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3027 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3028 SubIdx1 = 0; in storeRegPairToStackSlot()
3032 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3172 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3180 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3181 SubIdx1 = 0; in loadRegPairFromStackSlot()
3186 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3250 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3257 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3258 SubIdx1 = 0; in storeRegPairToStackSlot()
3262 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3402 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3410 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3411 SubIdx1 = 0; in loadRegPairFromStackSlot()
3416 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3641 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3648 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3649 SubIdx1 = 0; in storeRegPairToStackSlot()
3653 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3793 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3801 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3802 SubIdx1 = 0; in loadRegPairFromStackSlot()
3807 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3641 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3648 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3649 SubIdx1 = 0; in storeRegPairToStackSlot()
3653 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3793 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3801 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3802 SubIdx1 = 0; in loadRegPairFromStackSlot()
3807 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3641 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3648 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3649 SubIdx1 = 0; in storeRegPairToStackSlot()
3653 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3793 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3801 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3802 SubIdx1 = 0; in loadRegPairFromStackSlot()
3807 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3586 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3593 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3594 SubIdx1 = 0; in storeRegPairToStackSlot()
3598 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3738 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3746 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3747 SubIdx1 = 0; in loadRegPairFromStackSlot()
3752 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3641 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3648 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3649 SubIdx1 = 0; in storeRegPairToStackSlot()
3653 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3793 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3801 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3802 SubIdx1 = 0; in loadRegPairFromStackSlot()
3807 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3641 unsigned SubIdx0, unsigned SubIdx1, int FI, in storeRegPairToStackSlot() argument
3648 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
3649 SubIdx1 = 0; in storeRegPairToStackSlot()
3653 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
3793 unsigned SubIdx1, int FI, in loadRegPairFromStackSlot() argument
3801 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
3802 SubIdx1 = 0; in loadRegPairFromStackSlot()
3807 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()