Home
last modified time | relevance | path

Searched refs:SwitchRule (Results 1 – 16 of 16) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/passes/proc/
H A Dproc_mux.cc111 dict<RTLIL::SwitchRule*, pool<RTLIL::SigBit>, hash_ptr_ops> full_case_bits_cache;
112 dict<RTLIL::SwitchRule*, pool<int>, hash_ptr_ops> cache;
116 bool check(RTLIL::SwitchRule *sw) in check()
121 void insert(const RTLIL::CaseRule *cs, vector<RTLIL::SwitchRule*> &sw_stack) in insert()
142 vector<RTLIL::SwitchRule*> sw_stack; in insert()
147 void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs) in apply_attrs()
153 …L::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::Case… in gen_cmp()
255 …ompare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::Case… in append_pmux()
278 const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw) in get_full_case_bits()
321 …l_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool, hash_ptr… in signal_to_mux_tree() argument
[all …]
H A Dproc_rmdead.cc31 static bool can_use_fully_defined_pool(RTLIL::SwitchRule *sw) in can_use_fully_defined_pool()
81 void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter);
84 static void proc_rmdead_impl(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter) in proc_rmdead_impl()
124 void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter) in proc_rmdead()
H A Dproc_clean.cc32 void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &co… in proc_clean_switch()
142 RTLIL::SwitchRule *sw = cs->switches[i]; in proc_clean_case()
H A Dproc_prune.cc38 …pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::Sig… in do_switch()
/dports/cad/yosys/yosys-yosys-0.12/manual/
H A DCHAPTER_Verilog.tex586 The \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule}
597 Note that in contrast to this, the order within the \lstinline[language=C++]{RTLIL::SwitchRule} obj…
602 The whole \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree
615 … and the \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree
620 \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule}
705 \item A new \lstinline[language=C++]{RTLIL::SwitchRule} object is generated, the selection expressi…
707 …=C++]{subst_rvalue_to}) and added to the \lstinline[language=C++]{RTLIL::SwitchRule} object and the
737 new object and add the new object to the \lstinline[language=C++]{RTLIL::SwitchRule} created above.
813 one top-level \C{RTLIL::SwitchRule} for the reset path. After this pass the
815 \C{RTLIL::SwitchRule} has been removed.
[all …]
H A DCHAPTER_Overview.tex126 \node[entity] (switch) [fill=green!10, below of=case] {RTLIL::SwitchRule} edge [-latex] (case);
343 This RTLIL::Process contains two RTLIL::SyncRule objects, two RTLIL::SwitchRule
359 and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a
364 also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object is very similar to t…
366 which of its cases should be active. The RTLIL::SwitchRule object then contains one RTLIL::CaseRule
416 This pass has transformed the outer RTLIL::SwitchRule into a modified RTLIL::SyncRule object
H A DPRESENTATION_Prog.tex64 \node[entity] (switch) [fill=green!10, below of=case] {RTLIL::SwitchRule} edge [-latex] (case);
/dports/cad/yosys/yosys-yosys-0.12/backends/rtlil/
H A Drtlil_backend.h41 void dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw);
H A Drtlil_backend.cc199 void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *… in dump_proc_switch()
/dports/cad/yosys/yosys-yosys-0.12/frontends/rtlil/
H A Drtlil_parser.y39 std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
300 RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
/dports/cad/yosys/yosys-yosys-0.12/kernel/
H A Drtlil.h71 struct SwitchRule;
1558 std::vector<RTLIL::SwitchRule*> switches;
1569 struct RTLIL::SwitchRule : public RTLIL::AttrObject struct
1574 ~SwitchRule(); argument
1580 RTLIL::SwitchRule *clone() const;
1731 void RTLIL::SwitchRule::rewrite_sigspecs(T &functor) in rewrite_sigspecs()
1739 void RTLIL::SwitchRule::rewrite_sigspecs2(T &functor) in rewrite_sigspecs2()
H A Drtlil.cc4867 RTLIL::SwitchRule::~SwitchRule() in ~SwitchRule()
4873 bool RTLIL::SwitchRule::empty() const in empty()
4878 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const in clone()
4880 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule; in clone()
/dports/cad/yosys/yosys-yosys-0.12/passes/cmds/
H A Dshow.cc344 …void collect_proc_signals(RTLIL::SwitchRule *obj, std::set<RTLIL::SigSpec> &input_signals, std::se… in collect_proc_signals()
/dports/cad/yosys/yosys-yosys-0.12/frontends/ast/
H A Dgenrtlil.cc600 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; in processAst()
/dports/cad/yosys/yosys-yosys-0.12/backends/verilog/
H A Dverilog_backend.cc1850 void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw);
1879 void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) in dump_proc_switch()
/dports/cad/yosys/yosys-yosys-0.12/backends/cxxrtl/
H A Dcxxrtl_backend.cc1417 void dump_switch_rule(const RTLIL::SwitchRule *rule, bool for_debug = false) in dump_switch_rule()