/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 482 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 484 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 486 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 487 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 491 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 492 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 505 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 508 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 482 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 484 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 486 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 487 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 491 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 492 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 505 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 508 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 482 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 484 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 486 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 487 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 491 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 492 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 505 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 508 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 482 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 484 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 486 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 487 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 491 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 492 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 505 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 508 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 482 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 484 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 486 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 487 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 491 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 492 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 505 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 508 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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H A D | R600InstrInfo.h | 130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 458 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 460 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 462 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 464 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 465 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 469 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 470 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 478 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 483 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 486 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 480 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 482 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 484 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 486 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 487 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 491 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 492 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 500 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 505 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 508 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 481 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 483 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 485 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 487 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 488 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 492 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 493 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 501 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 506 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 509 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 481 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 483 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 485 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 487 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 488 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 492 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 493 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 501 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 506 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 509 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 481 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 483 assert(Idx < SwzCandidate.size()); 485 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) 487 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { 488 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; 492 int NextSwizzle = SwzCandidate[ResetIdx] + 1; 493 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; 501 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 506 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); 509 } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution() argument 459 assert(Idx < SwzCandidate.size()); in NextPossibleSolution() 461 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution() 463 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { in NextPossibleSolution() 464 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution() 468 int NextSwizzle = SwzCandidate[ResetIdx] + 1; in NextPossibleSolution() 469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution() 477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot() argument 482 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); in FindSwizzleForVectorSlot() 485 } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); in FindSwizzleForVectorSlot()
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