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Searched refs:TCON_BIT_CH (Results 1 – 25 of 56) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) in nx_tieoff_set()
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in nx_tieoff_get()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in nx_tieoff_get()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in nx_tieoff_get()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in nx_tieoff_get()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch));
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/mach-nexell/
H A Dtimer.c49 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) macro
83 val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); in timer_start()
84 writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); in timer_start()
86 val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); in timer_start()
87 val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); in timer_start()
99 val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); in timer_stop()

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