/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2096 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/net/ipxe/ipxe-2265a65/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1939 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 1940 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 1954 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1956 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 1969 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 1972 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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H A D | tg3.h | 2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/broadcom/ |
H A D | tg3.h | 2069 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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H A D | tg3.c | 6456 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) in tg3_dump_state() 9936 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 9937 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 9951 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 9953 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 9973 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 9976 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/broadcom/ |
H A D | tg3.h | 2069 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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H A D | tg3.c | 6456 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) in tg3_dump_state() 9936 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 9937 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 9951 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 9953 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 9973 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 9976 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/broadcom/ |
H A D | tg3.h | 2069 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 macro
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H A D | tg3.c | 6456 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) in tg3_dump_state() 9936 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw() 9937 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, in tg3_reset_hw() 9951 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 9953 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, in tg3_reset_hw() 9973 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw() 9976 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, in tg3_reset_hw()
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