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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h345 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
353 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
369 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
479 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
483 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
511 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
516 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
546 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
580 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
H A DSIInstrFormats.td145 let TSFlags{0} = SALU;
146 let TSFlags{1} = VALU;
148 let TSFlags{2} = SOP1;
149 let TSFlags{3} = SOP2;
150 let TSFlags{4} = SOPC;
151 let TSFlags{5} = SOPK;
152 let TSFlags{6} = SOPP;
154 let TSFlags{7} = VOP1;
155 let TSFlags{8} = VOP2;
156 let TSFlags{9} = VOPC;
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DSIInstrInfo.h345 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
353 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
369 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
479 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
483 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
511 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
516 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
546 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
580 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
H A DSIInstrFormats.td145 let TSFlags{0} = SALU;
146 let TSFlags{1} = VALU;
148 let TSFlags{2} = SOP1;
149 let TSFlags{3} = SOP2;
150 let TSFlags{4} = SOPC;
151 let TSFlags{5} = SOPK;
152 let TSFlags{6} = SOPP;
154 let TSFlags{7} = VOP1;
155 let TSFlags{8} = VOP2;
156 let TSFlags{9} = VOPC;
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h345 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
353 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
369 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
479 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
483 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
511 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
516 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
546 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
580 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
H A DSIInstrFormats.td145 let TSFlags{0} = SALU;
146 let TSFlags{1} = VALU;
148 let TSFlags{2} = SOP1;
149 let TSFlags{3} = SOP2;
150 let TSFlags{4} = SOPC;
151 let TSFlags{5} = SOPK;
152 let TSFlags{6} = SOPP;
154 let TSFlags{7} = VOP1;
155 let TSFlags{8} = VOP2;
156 let TSFlags{9} = VOPC;
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h356 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
364 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
380 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
490 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
494 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
522 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
527 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
557 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
591 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
623 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
H A DSIInstrFormats.td145 let TSFlags{0} = SALU;
146 let TSFlags{1} = VALU;
148 let TSFlags{2} = SOP1;
149 let TSFlags{3} = SOP2;
150 let TSFlags{4} = SOPC;
151 let TSFlags{5} = SOPK;
152 let TSFlags{6} = SOPP;
154 let TSFlags{7} = VOP1;
155 let TSFlags{8} = VOP2;
156 let TSFlags{9} = VOPC;
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h345 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
353 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
369 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
479 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
483 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
511 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
516 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
546 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
580 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h345 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
353 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
369 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
479 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
483 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
511 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
516 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
546 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
580 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td139 let TSFlags{0} = SALU;
140 let TSFlags{1} = VALU;
142 let TSFlags{2} = SOP1;
143 let TSFlags{3} = SOP2;
144 let TSFlags{4} = SOPC;
145 let TSFlags{5} = SOPK;
146 let TSFlags{6} = SOPP;
148 let TSFlags{7} = VOP1;
149 let TSFlags{8} = VOP2;
150 let TSFlags{9} = VOPC;
[all …]
H A DSIInstrInfo.h337 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
345 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
361 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
471 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
475 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
503 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
508 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
538 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
546 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
578 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td139 let TSFlags{0} = SALU;
140 let TSFlags{1} = VALU;
142 let TSFlags{2} = SOP1;
143 let TSFlags{3} = SOP2;
144 let TSFlags{4} = SOPC;
145 let TSFlags{5} = SOPK;
146 let TSFlags{6} = SOPP;
148 let TSFlags{7} = VOP1;
149 let TSFlags{8} = VOP2;
150 let TSFlags{9} = VOPC;
[all …]
H A DSIInstrInfo.h337 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
345 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
361 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
471 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
475 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
503 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
508 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
538 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
546 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
578 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/
H A DSIInstrInfo.h305 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
313 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
329 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
337 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
431 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
435 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
461 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
475 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
483 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
515 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/
H A DSIInstrInfo.h329 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
337 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
353 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
361 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
463 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
467 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
495 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
514 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
522 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
554 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
292 let TSFlags{6-0} = Type.Value;
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
167 let TSFlags{62} = CVINew;
170 let TSFlags{63} = isCVI;
293 let TSFlags{6-0} = Type.Value;
[all …]

12345678910>>...65