/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | s390-opc.c | 193 #define U4_20 57 /* 4 bit unsigned value starting at 20 */ macro 342 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 343 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 344 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 345 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 346 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 347 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 355 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 356 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 357 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | s390-opc.c | 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ macro 357 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 358 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 359 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 360 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 361 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ 362 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | s390-opc.c | 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ macro 357 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 358 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 359 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 360 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 361 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ 362 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | s390-opc.c | 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ macro 357 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 358 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 359 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 360 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 361 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ 362 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | s390-opc.c | 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ macro 357 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 358 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 359 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 360 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 361 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ 362 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | s390-opc.c | 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ macro 352 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 353 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 354 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 355 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 356 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 357 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 364 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 365 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 366 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | s390-opc.c | 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ macro 352 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 353 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 354 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 355 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 356 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 357 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 364 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 365 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 366 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/s390/kernel/ |
H A D | dis.c | 113 U4_20, /* 4 bit unsigned value starting at 20 */ enumerator 175 [U4_20] = { 4, 20, 0 }, 230 [INSTR_RRF_0UFF] = { F_24, F_28, U4_20, 0, 0, 0 }, 231 [INSTR_RRF_0URF] = { R_24, F_28, U4_20, 0, 0, 0 }, 235 [INSTR_RRF_FFRU] = { F_24, F_16, R_28, U4_20, 0, 0 }, 236 [INSTR_RRF_FUFF] = { F_24, F_16, F_28, U4_20, 0, 0 }, 237 [INSTR_RRF_FUFF2] = { F_24, F_28, F_16, U4_20, 0, 0 }, 240 [INSTR_RRF_RURR] = { R_24, R_28, R_16, U4_20, 0, 0 }, 241 [INSTR_RRF_RURR2] = { R_24, R_16, R_28, U4_20, 0, 0 }, 246 [INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 }, [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/s390/kernel/ |
H A D | dis.c | 113 U4_20, /* 4 bit unsigned value starting at 20 */ enumerator 175 [U4_20] = { 4, 20, 0 }, 230 [INSTR_RRF_0UFF] = { F_24, F_28, U4_20, 0, 0, 0 }, 231 [INSTR_RRF_0URF] = { R_24, F_28, U4_20, 0, 0, 0 }, 235 [INSTR_RRF_FFRU] = { F_24, F_16, R_28, U4_20, 0, 0 }, 236 [INSTR_RRF_FUFF] = { F_24, F_16, F_28, U4_20, 0, 0 }, 237 [INSTR_RRF_FUFF2] = { F_24, F_28, F_16, U4_20, 0, 0 }, 240 [INSTR_RRF_RURR] = { R_24, R_28, R_16, U4_20, 0, 0 }, 241 [INSTR_RRF_RURR2] = { R_24, R_16, R_28, U4_20, 0, 0 }, 246 [INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 }, [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/s390/kernel/ |
H A D | dis.c | 113 U4_20, /* 4 bit unsigned value starting at 20 */ enumerator 175 [U4_20] = { 4, 20, 0 }, 230 [INSTR_RRF_0UFF] = { F_24, F_28, U4_20, 0, 0, 0 }, 231 [INSTR_RRF_0URF] = { R_24, F_28, U4_20, 0, 0, 0 }, 235 [INSTR_RRF_FFRU] = { F_24, F_16, R_28, U4_20, 0, 0 }, 236 [INSTR_RRF_FUFF] = { F_24, F_16, F_28, U4_20, 0, 0 }, 237 [INSTR_RRF_FUFF2] = { F_24, F_28, F_16, U4_20, 0, 0 }, 240 [INSTR_RRF_RURR] = { R_24, R_28, R_16, U4_20, 0, 0 }, 241 [INSTR_RRF_RURR2] = { R_24, R_16, R_28, U4_20, 0, 0 }, 246 [INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 }, [all …]
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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | s390-opc.c | 153 #define U4_20 41 /* 4 bit unsigned value starting at 20 */ macro 275 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 276 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 277 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 282 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 283 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 284 #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ 288 #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ 289 #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | s390-opc.c | 117 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 197 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 198 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | s390-opc.c | 117 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 197 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 198 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | s390-opc.c | 117 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 197 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 198 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | s390-opc.c | 117 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 206 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 207 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | s390-dis.c | 507 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 605 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 606 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 610 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 611 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 612 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | s390.c | 555 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 673 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 674 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 678 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 679 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 680 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | s390.c | 554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ macro 672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
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