| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 240 UADDV_PRED, enumerator
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| H A D | AArch64ISelLowering.cpp | 1720 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
9955 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
13041 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
13045 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16516 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
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| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 242 UADDV_PRED, enumerator
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| H A D | AArch64ISelLowering.cpp | 1847 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10370 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
13613 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
13617 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
17170 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
17173 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
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| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 242 UADDV_PRED, enumerator
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| H A D | AArch64ISelLowering.cpp | 1847 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10370 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
13613 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
13617 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
17170 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
17173 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 254 UADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2019 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10965 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
14389 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
14393 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16527 case AArch64ISD::UADDV_PRED: in isLanes1toNKnownZero()
18373 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
18376 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 254 UADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2019 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10965 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
14389 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
14393 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16527 case AArch64ISD::UADDV_PRED: in isLanes1toNKnownZero()
18373 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
18376 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 254 UADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2019 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10965 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
14389 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
14393 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16527 case AArch64ISD::UADDV_PRED: in isLanes1toNKnownZero()
18373 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
18376 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 254 UADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2019 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10965 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
14389 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
14393 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16527 case AArch64ISD::UADDV_PRED: in isLanes1toNKnownZero()
18373 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
18376 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 254 UADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2019 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
10965 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
14389 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
14393 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16527 case AArch64ISD::UADDV_PRED: in isLanes1toNKnownZero()
18373 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
18376 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 254 UADDV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2046 MAKE_CASE(AArch64ISD::UADDV_PRED) in getTargetNodeName()
11198 return LowerReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG); in LowerVECREDUCE()
14688 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
14692 return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); in performIntrinsicCombine()
16827 case AArch64ISD::UADDV_PRED: in isLanes1toNKnownZero()
18690 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : in LowerReductionToSVE()
18693 if (SrcVT.isFixedLengthVector() || Opcode == AArch64ISD::UADDV_PRED) in LowerReductionToSVE()
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| H A D | AArch64SVEInstrInfo.td | 156 def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
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