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Searched refs:UFCON_FIFO_ENABLE (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu/qemu-6.2.0/hw/char/
H A Dexynos4210_uart.c96 #define UFCON_FIFO_ENABLE 0x1 macro
291 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
503 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
557 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_can_receive()
569 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu60/qemu-6.0.0/hw/char/
H A Dexynos4210_uart.c96 #define UFCON_FIFO_ENABLE 0x1 macro
291 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
503 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
557 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_can_receive()
569 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/char/
H A Dexynos4210_uart.c96 #define UFCON_FIFO_ENABLE 0x1 macro
291 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
503 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
557 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_can_receive()
569 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu42/qemu-4.2.1/hw/char/
H A Dexynos4210_uart.c130 #define UFCON_FIFO_ENABLE 0x1 macro
286 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
451 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
506 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/char/
H A Dexynos4210_uart.c127 #define UFCON_FIFO_ENABLE 0x1 macro
283 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
448 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
503 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/char/
H A Dexynos4210_uart.c130 #define UFCON_FIFO_ENABLE 0x1 macro
286 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
451 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
506 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu5/qemu-5.2.0/hw/char/
H A Dexynos4210_uart.c95 #define UFCON_FIFO_ENABLE 0x1 macro
290 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
502 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
563 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/char/
H A Dexynos4210_uart.c93 #define UFCON_FIFO_ENABLE 0x1 macro
289 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
501 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
562 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/char/
H A Dexynos4210_uart.c93 #define UFCON_FIFO_ENABLE 0x1 macro
289 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
501 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
562 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()