| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 159 UMAXV_PRED, enumerator
|
| H A D | AArch64SVEInstrInfo.td | 60 def AArch64umaxv_pred : SDNode<"AArch64ISD::UMAXV_PRED", SDT_AArch64Reduce>;
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 159 UMAXV_PRED, enumerator
|
| H A D | AArch64SVEInstrInfo.td | 60 def AArch64umaxv_pred : SDNode<"AArch64ISD::UMAXV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 159 UMAXV_PRED, enumerator
|
| H A D | AArch64SVEInstrInfo.td | 60 def AArch64umaxv_pred : SDNode<"AArch64ISD::UMAXV_PRED", SDT_AArch64Reduce>;
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 203 UMAXV_PRED, enumerator
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 203 UMAXV_PRED, enumerator
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 242 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1722 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
9965 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
13049 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 244 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 1849 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
10380 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
13621 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 244 UMAXV_PRED, enumerator
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 256 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2021 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
10975 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
14397 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
16528 case AArch64ISD::UMAXV_PRED: in isLanes1toNKnownZero()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 256 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2021 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
10975 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
14397 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
16528 case AArch64ISD::UMAXV_PRED: in isLanes1toNKnownZero()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 256 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2021 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
10975 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
14397 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
16528 case AArch64ISD::UMAXV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 256 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2021 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
10975 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
14397 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
16528 case AArch64ISD::UMAXV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 256 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2021 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
10975 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
14397 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
16528 case AArch64ISD::UMAXV_PRED: in isLanes1toNKnownZero()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 256 UMAXV_PRED, enumerator
|
| H A D | AArch64ISelLowering.cpp | 2048 MAKE_CASE(AArch64ISD::UMAXV_PRED) in getTargetNodeName()
11208 return LowerReductionToSVE(AArch64ISD::UMAXV_PRED, Op, DAG); in LowerVECREDUCE()
14696 return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); in performIntrinsicCombine()
16828 case AArch64ISD::UMAXV_PRED: in isLanes1toNKnownZero()
|