| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 31 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
79 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
105 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 31 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
79 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
105 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 31 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
79 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
105 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 31 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
79 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
105 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) macro
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_on()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in rcar_gen2_phy_phy_power_off()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/phy/ |
| H A D | phy-rcar-gen2.c | 34 #define USBHS_UGCTRL_PLLRESET BIT(0) in ipq4019_ss_phy_power_off()
82 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET); in ipq4019_hs_phy_power_off()
108 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET);
|