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Searched refs:UUNPKHI (Results 1 – 25 of 75) sorted by relevance

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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.h204 UUNPKHI, enumerator
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h204 UUNPKHI, enumerator
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h204 UUNPKHI, enumerator
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h250 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp1543 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3188 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10979 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
13679 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
13681 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
14315 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.h250 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp1546 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3192 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
11011 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
13714 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
13716 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
14350 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h286 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp1799 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3484 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9541 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
9584 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
11878 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
13681 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
14808 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
14810 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
15453 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
16257 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h288 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp1926 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3582 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9956 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
9999 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
12447 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
14253 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
15425 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
15427 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
16079 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
16911 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h288 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp1926 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3582 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9956 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
9999 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
12447 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
14253 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
15425 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
15427 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
16079 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
16911 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h302 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp2103 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3904 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10553 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
10596 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
13161 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
15017 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
16342 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
16344 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
17135 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
18085 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.h302 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp2103 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3904 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10553 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
10596 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
13161 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
15017 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
16342 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
16344 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
17135 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
18085 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h302 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp2103 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3904 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10553 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
10596 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
13161 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
15017 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
16342 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
16344 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
17135 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
18085 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h302 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp2103 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3904 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10553 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
10596 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
13161 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
15017 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
16342 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
16344 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
17135 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
18085 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h302 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp2103 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3904 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10553 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
10596 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
13161 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
15017 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
16342 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
16344 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
17135 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
18085 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h302 UUNPKHI, enumerator
H A DAArch64ISelLowering.cpp2130 MAKE_CASE(AArch64ISD::UUNPKHI) in getTargetNodeName()
3978 return DAG.getNode(AArch64ISD::UUNPKHI, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10786 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
10829 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerDIV()
13415 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSVEAndCombine()
15318 if (Op1.getOpcode() == AArch64ISD::UUNPKHI) { in performUzpCombine()
16642 if (Opc == AArch64ISD::UUNPKHI || Opc == AArch64ISD::UUNPKLO) { in performSignExtendInRegCombine()
16644 unsigned SOpc = Opc == AArch64ISD::UUNPKHI ? AArch64ISD::SUNPKHI in performSignExtendInRegCombine()
17437 unsigned Opcode = (Index == 0) ? AArch64ISD::UUNPKLO : AArch64ISD::UUNPKHI; in ReplaceExtractSubVectorResults()
18402 unsigned UnpkHi = Signed ? AArch64ISD::SUNPKHI : AArch64ISD::UUNPKHI; in LowerFixedLengthVectorIntDivideToSVE()

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