/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | vcn_v1_0.c | 859 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode() 864 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode() 1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode() 1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle() 1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle() 1342 UVD_STATUS__IDLE); in vcn_v1_0_wait_for_idle()
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H A D | amdgpu_vcn.h | 177 UVD_STATUS__IDLE = 0x2, enumerator
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H A D | vcn_v3_0.c | 1566 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop() 2154 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle() 2169 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle() 2170 UVD_STATUS__IDLE); in vcn_v3_0_wait_for_idle() 2190 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()
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H A D | vcn_v2_0.c | 1137 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop() 1273 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle() 1281 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle() 1282 UVD_STATUS__IDLE); in vcn_v2_0_wait_for_idle()
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H A D | vcn_v2_5.c | 1339 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop() 1749 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle() 1763 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle() 1764 UVD_STATUS__IDLE); in vcn_v2_5_wait_for_idle()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | vcn_v1_0.c | 859 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode() 864 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode() 1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode() 1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle() 1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle() 1342 UVD_STATUS__IDLE); in vcn_v1_0_wait_for_idle()
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H A D | amdgpu_vcn.h | 177 UVD_STATUS__IDLE = 0x2, enumerator
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H A D | vcn_v3_0.c | 1566 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop() 2154 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle() 2169 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle() 2170 UVD_STATUS__IDLE); in vcn_v3_0_wait_for_idle() 2190 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()
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H A D | vcn_v2_0.c | 1137 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop() 1273 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle() 1281 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle() 1282 UVD_STATUS__IDLE); in vcn_v2_0_wait_for_idle()
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H A D | vcn_v2_5.c | 1339 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop() 1749 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle() 1763 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle() 1764 UVD_STATUS__IDLE); in vcn_v2_5_wait_for_idle()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/ |
H A D | vcn_v1_0.c | 859 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode() 864 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode() 1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode() 1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle() 1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle() 1342 UVD_STATUS__IDLE); in vcn_v1_0_wait_for_idle()
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H A D | amdgpu_vcn.h | 177 UVD_STATUS__IDLE = 0x2, enumerator
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H A D | vcn_v3_0.c | 1566 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop() 2154 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle() 2169 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle() 2170 UVD_STATUS__IDLE); in vcn_v3_0_wait_for_idle() 2190 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()
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H A D | vcn_v2_0.c | 1137 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop() 1273 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle() 1281 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle() 1282 UVD_STATUS__IDLE); in vcn_v2_0_wait_for_idle()
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H A D | vcn_v2_5.c | 1339 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop() 1749 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle() 1763 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle() 1764 UVD_STATUS__IDLE); in vcn_v2_5_wait_for_idle()
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