| /dports/science/R-cran-Epi/Epi/R/ |
| H A D | float.R | 19 V00 <- sum(R)/(m * (m-1)) functionVar
21 fv <- c(V00, V00 - 2 * V10 + diag(V))
29 V00 <- as.vector(1/S + t(w1) %*% V %*% w1)
32 fv <- c(V00, V00 - 2 * V10 + diag(V))
|
| /dports/devel/z88dk/z88dk/examples/zxvgs/ |
| H A D | Makefile | 3 all: info.V00
6 info.V00: info.c
10 rm -f *.bin *.i *.asm *.op* *.o *~ zcc_opt.def *.V00
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/mlir/test/Target/ |
| H A D | arm-neon.mlir | 6 …// CHECK-NEXT: %[[V00:.*]] = shufflevector <8 x i16> %3, <8 x i16> %[[V0]], <4 x i32> <i32 3, i32 …
10 … %[[V1:.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %[[V00]], <4 x i16> %[[V00]])
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/mlir/test/Target/ |
| H A D | arm-neon.mlir | 6 …// CHECK-NEXT: %[[V00:.*]] = shufflevector <8 x i16> %3, <8 x i16> %[[V0]], <4 x i32> <i32 3, i32 …
10 … %[[V1:.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %[[V00]], <4 x i16> %[[V00]])
|
| /dports/cad/opencascade/opencascade-7.6.0/src/BRepLib/ |
| H A D | BRepLib_MakeFace.cxx | 615 TopoDS_Vertex V00,V10,V11,V01; in Init() local
618 if (!vmininf) B.MakeVertex(V00,S->Value(UMin,VMin), Max(uminTol, vminTol)); in Init()
627 V10 = V00; in Init()
632 V01 = V00; in Init()
636 if (Dumin) V00 = V01; in Init()
638 if (Dvmin) V00 = V10; in Init()
670 V00.Orientation(TopAbs_FORWARD); in Init()
671 B.Add(eumin,V00); in Init()
713 V00.Orientation(TopAbs_FORWARD); in Init()
714 B.Add(evmin,V00); in Init()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/mlir/test/Target/LLVMIR/ |
| H A D | arm-neon.mlir | 6 …// CHECK-NEXT: %[[V00:.*]] = shufflevector <8 x i16> %3, <8 x i16> %[[V0]], <4 x i32> <i32 3, i32 …
10 … %[[V1:.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %[[V00]], <4 x i16> %[[V00]])
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/mlir/test/Target/LLVMIR/ |
| H A D | arm-neon.mlir | 6 …// CHECK-NEXT: %[[V00:.*]] = shufflevector <8 x i16> %3, <8 x i16> %[[V0]], <4 x i32> <i32 3, i32 …
10 … %[[V1:.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %[[V00]], <4 x i16> %[[V00]])
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/mlir/test/Target/LLVMIR/ |
| H A D | arm-neon.mlir | 6 …// CHECK-NEXT: %[[V00:.*]] = shufflevector <8 x i16> %3, <8 x i16> %[[V0]], <4 x i32> <i32 3, i32 …
10 … %[[V1:.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %[[V00]], <4 x i16> %[[V00]])
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/mlir/test/Target/LLVMIR/ |
| H A D | arm-neon.mlir | 6 …// CHECK-NEXT: %[[V00:.*]] = shufflevector <8 x i16> %3, <8 x i16> %[[V0]], <4 x i32> <i32 3, i32 …
10 … %[[V1:.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %[[V00]], <4 x i16> %[[V00]])
|
| /dports/science/openbabel/openbabel-3.1.1/test/pdb_ligands_sdf/ |
| H A D | 2v00_v15.sdf | 3 Coordinates from PDB:2V00:A:1336 Model:1 without hydrogens
78 2V00
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/autohvx/ |
| H A D | isel-expand-unaligned-loads.ll | 4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
6 ; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
|