/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 224 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1724 case ARMISD::VADDVps: return "ARMISD::VADDVps"; in getTargetNodeName() 15047 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 15056 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 692 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 224 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1731 case ARMISD::VADDVps: return "ARMISD::VADDVps"; in getTargetNodeName() 15093 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 15104 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 692 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 224 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1731 case ARMISD::VADDVps: return "ARMISD::VADDVps"; in getTargetNodeName() 15093 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 15104 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1735 MAKE_CASE(ARMISD::VADDVps) in getTargetNodeName() 16144 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 16153 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 692 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1735 MAKE_CASE(ARMISD::VADDVps) in getTargetNodeName() 16144 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 16153 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 692 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1735 MAKE_CASE(ARMISD::VADDVps) in getTargetNodeName() 16144 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 16153 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 692 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1748 MAKE_CASE(ARMISD::VADDVps) in getTargetNodeName() 16470 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 16479 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 693 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1735 MAKE_CASE(ARMISD::VADDVps) in getTargetNodeName() 16144 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 16153 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 692 def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1735 MAKE_CASE(ARMISD::VADDVps) in getTargetNodeName() 16144 return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); in PerformVECREDUCE_ADDCombine() 16153 DAG.getNode(ARMISD::VADDVps, dl, MVT::i32, A, Mask)); in PerformVECREDUCE_ADDCombine()
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