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Searched refs:VHDL_BINOP_AND (Results 1 – 4 of 4) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dexpr.cc397 result = translate_numeric(lhs, rhs, VHDL_BINOP_AND); in translate_binary()
400 result = translate_logical(lhs, rhs, VHDL_BINOP_AND); in translate_binary()
H A Dlogic.cc237 return inputs_to_expr(scope, VHDL_BINOP_AND, log); in translate_logic_inputs()
H A Dvhdl_syntax.hh90 VHDL_BINOP_AND = 0, enumerator
H A Dstmt.cc1503 new vhdl_binop_expr(VHDL_BINOP_AND, vhdl_type::boolean()); in draw_casezx()