Searched refs:VHDL_BINOP_LEQ (Results 1 – 2 of 2) sorted by relevance
| /dports/cad/iverilog/verilog-11.0/tgt-vhdl/ | ||
| H A D | expr.cc | 421 result = translate_relation(lhs, rhs, VHDL_BINOP_LEQ); in translate_binary() |
| H A D | vhdl_syntax.hh | 99 VHDL_BINOP_LEQ, enumerator |