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Searched refs:VHDL_PORT_BUFFER (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.cc465 case VHDL_PORT_BUFFER: in emit()
477 mode_ = VHDL_PORT_BUFFER; in ensure_readable()
486 return mode_ != VHDL_PORT_OUT && mode_ != VHDL_PORT_BUFFER; in is_readable()
H A Dvhdl_syntax.hh714 VHDL_PORT_BUFFER enumerator