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Searched refs:VHDL_PORT_INOUT (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.hh713 VHDL_PORT_INOUT, enumerator
H A Dscope.cc631 (new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_INOUT)); in declare_one_signal()
H A Dvhdl_syntax.cc462 case VHDL_PORT_INOUT: in emit()