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Searched refs:VHDL_PORT_OUT (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.cc459 case VHDL_PORT_OUT: in emit()
476 if (mode_ == VHDL_PORT_OUT) in ensure_readable()
486 return mode_ != VHDL_PORT_OUT && mode_ != VHDL_PORT_BUFFER; in is_readable()
H A Dvhdl_syntax.hh712 VHDL_PORT_OUT, enumerator
H A Dscope.cc603 new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT); in declare_one_signal()