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Searched refs:VHDL_UNARYOP_NOT (Results 1 – 5 of 5) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dexpr.cc163 return new vhdl_unaryop_expr(VHDL_UNARYOP_NOT, result, in translate_reduction()
182 (VHDL_UNARYOP_NOT, operand, new vhdl_type(*operand->get_type())); in translate_unary()
H A Dlogic.cc235 return input_to_expr(scope, VHDL_UNARYOP_NOT, log); in translate_logic_inputs()
H A Dlpm.cc170 (VHDL_UNARYOP_NOT, result, vhdl_type::std_logic()); in reduction_lpm_to_expr()
H A Dvhdl_syntax.hh139 VHDL_UNARYOP_NOT, enumerator
H A Dvhdl_syntax.cc913 case VHDL_UNARYOP_NOT: in emit()