/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1740 case ARMISD::VMLALVps: return "ARMISD::VMLALVps"; in getTargetNodeName() 12454 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 12458 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 15082 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1160 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1747 case ARMISD::VMLALVps: return "ARMISD::VMLALVps"; in getTargetNodeName() 12459 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 12463 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 15134 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1160 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 240 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1747 case ARMISD::VMLALVps: return "ARMISD::VMLALVps"; in getTargetNodeName() 12459 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 12463 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 15134 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1751 MAKE_CASE(ARMISD::VMLALVps) in getTargetNodeName() 13139 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 13143 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 16184 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1160 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1751 MAKE_CASE(ARMISD::VMLALVps) in getTargetNodeName() 13139 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 13143 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 16184 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1160 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1751 MAKE_CASE(ARMISD::VMLALVps) in getTargetNodeName() 13139 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 13143 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 16184 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1160 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1764 MAKE_CASE(ARMISD::VMLALVps) in getTargetNodeName() 13375 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 13379 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 16443 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1162 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1751 MAKE_CASE(ARMISD::VMLALVps) in getTargetNodeName() 13139 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 13143 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 16184 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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H A D | ARMInstrMVE.td | 1160 def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask enumerator
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H A D | ARMISelLowering.cpp | 1751 MAKE_CASE(ARMISD::VMLALVps) in getTargetNodeName() 13139 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce() 13143 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce() 16184 return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); in PerformVECREDUCE_ADDCombine()
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