/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 23 # CHECK: %6:spr = VMOVSR %5, 14, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 66 %5:spr = VMOVSR %4, 14, $noreg 85 # CHECK: %5:spr = VMOVSR %4, 14, $noreg 102 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmpe.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | fcmp-xo.ll | 2 …=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 43 ; VMOVSR-LABEL: float128: 44 ; VMOVSR: @ %bb.0: 45 ; VMOVSR-NEXT: mov.w r0, #1124073472 46 ; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47 ; VMOVSR-NEXT: vmov s2, r0 48 ; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49 ; VMOVSR-NEXT: vcmp.f32 s2, s0 50 ; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51 ; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 [all …]
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H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/ARM/ |
H A D | peephole-phi.mir | 27 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 42 %6:spr = VMOVSR %5, 14, $noreg 80 %5:spr = VMOVSR %4, 14, $noreg 103 ; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg 116 %5:spr = VMOVSR %4, 14, $noreg
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