1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Midhunchandra Kodiyath <midhunchandra.kodiyath@intel.com> 26 * 27 */ 28 29 #ifndef _MEDIA__DRIVER_DEFINES_H 30 #define _MEDIA__DRIVER_DEFINES_H 31 #include <stdbool.h> 32 #include <stdint.h> 33 34 #define FRAME_TYPE_I 1 35 #define FRAME_TYPE_P 2 36 #define FRAME_TYPE_B 3 37 38 39 #define CODEC_H264 0 40 #define CODEC_MPEG2 1 41 #define CODEC_VP8 3 42 43 44 #define VP8_DELIMITER0 0x00 45 #define VP8_DELIMITER1 0x00 46 #define VP8_DELIMITER2 0x00 47 #define VP8_DELIMITER3 0x00 48 #define VP8_DELIMITER4 0x0 49 50 #define NUM_SLICES 10 51 52 #define MEDIA_GEN_MAX_PROFILES 16 // VAProfileH264Baseline, VAProfileH264Main,VAProfileH264High,VAProfileH264ConstrainedBaseline VAProfileMPEG2Main, VAProfileMPEG2Simple, VAProfileHEVCMain and VAProfileNone 53 #define MEDIA_GEN_MAX_ENTRYPOINTS 4 // VAEntrypointHybridEnc 54 #define MEDIA_GEN_MAX_CONFIG_ATTRIBUTES 46 // VAConfigAttribRTFormat plus VAConfigAttribRateControl 55 #define MEDIA_GEN_MAX_IMAGE_FORMATS 2 56 #define MEDIA_GEN_MAX_SUBPIC_FORMATS 4 // no sub-pic blending support, still set to 4 for further implementation 57 #define MEDIA_GEN_MAX_SUBPIC 4 58 #define MEDIA_GEN_MAX_DISPLAY_ATTRIBUTES 4 // Use the same value as I965 59 #define MEDIA_GEN_MAX_ATTRIBS_TYPE 4 //VAConfigAttribRTFormat, VAConfigAttribRateControl, VAConfigAttribDecSliceMode, VAConfigAttribEncPackedHeaders 60 61 // 62 #define I965_MAX_SUBPIC_SUM 4 63 64 #define BUFFER_ID_OFFSET 0x08000000 65 // 66 #define MAX_GPE_KERNELS 32 67 #define MAX_INTERFACE_DESC_GEN6 MAX_GPE_KERNELS 68 #define CURBE_ALLOCATION_SIZE 0X35 //37 69 #define CURBE_TOTAL_DATA_LENGTH 0x1C0 //0x140 //(4 * 35) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */ 70 #define CURBE_URB_ENTRY_LENGTH 4 71 // 72 #define SUBSAMPLE_YUV400 0 73 #define SUBSAMPLE_YUV420 1 74 #define SUBSAMPLE_YUV422H 2 75 #define SUBSAMPLE_YUV422V 3 76 #define SUBSAMPLE_YUV444 4 77 #define SUBSAMPLE_YUV411 5 78 #define SUBSAMPLE_RGBX 6 79 #define SUBSAMPLE_P208 7 80 #define SURFACE_REFERENCED (1 << 0) 81 #define SURFACE_DISPLAYED (1 << 1) 82 #define SURFACE_DERIVED (1 << 2) 83 84 #define I965_SURFACE_MEM_NATIVE 0 85 #define I965_SURFACE_MEM_GEM_FLINK 1 86 #define I965_SURFACE_MEM_DRM_PRIME 2 87 88 #define INTEL_STR_DRIVER_VENDOR "Intel" 89 #define INTEL_STR_DRIVER_NAME "hybrid" 90 91 typedef double DOUBLE; 92 typedef float FLOAT; 93 typedef unsigned long ULONG; 94 typedef unsigned int DWORD; 95 typedef unsigned int UINT; 96 typedef unsigned short UINT16; 97 typedef short INT16; 98 typedef int INT; 99 typedef unsigned char BYTE; 100 typedef char CHAR; 101 typedef bool BOOL; 102 typedef bool STATUS; 103 typedef void VOID; 104 105 #define TRUE 1 106 #define FALSE 0 107 #define ERROR -1 108 109 110 /*debug enable*/ 111 #define SUCCESS 1 112 #define FAILED 0 113 //#define DEBUG 114 //#define DEBUG_LEVEL1 115 #define CODEC_DEC 0 116 #define CODEC_ENC 1 117 #define CODEC_PROC 2 118 119 120 //VP* 121 122 // HME 123 #define SCALE_FACTOR_2x 2 124 #define SCALE_FACTOR_4x 4 125 #define SCALE_FACTOR_16x 16 126 #define SCALE_FACTOR_32x 32 127 128 //BRC 129 #define ENCODE_BRC_KBPS 1000 130 #define BRC_IMG_STATE_SIZE_PER_PASS 128 131 132 #define WIDTH_IN_MACROBLOCKS(width) (((width) + (16 - 1)) / 16) 133 #define HEIGHT_IN_MACROBLOCKS(height) (((height) + (16 - 1)) / 16) 134 135 136 #define SCOREBOARD_STALLING 0 137 #define SCOREBOARD_NON_STALLING 1 138 139 //I965 DEFINES... 140 #define MEDIA_SURFACE_1D 0 141 #define MEDIA_SURFACE_2D 1 142 #define MEDIA__SURFACE_3D 2 143 #define MEDIA__SURFACE_CUBE 3 144 #define MEDIA_SURFACE_BUFFER 4 145 #define MEDIA_SURFACE_NULL 7 146 147 #define STATE_SURFACEFORMAT_R32_UNORM 0x0F1 148 #define STATE_SURFACEFORMAT_R8_UNORM 0x140 149 #define STATE_SURFACEFORMAT_R16_UINT 0x10D 150 #define STATE_SURFACEFORMAT_RAW 0x1FF 151 #define STATE_SURFACEFORMAT_R32_UINT 0x0D7 152 153 #define MEDIA_TILEWALK_XMAJOR 0 154 #define MEDIA_TILEWALK_YMAJOR 1 155 156 #define MAX_MEDIA_SURFACES_GEN6 34 157 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 sizeof(struct gen7_surface_state) /*ALIGN(sizeof(struct gen7_surface_state), 32) */ 158 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 sizeof(struct gen7_surface_state2) /*ALIGN(sizeof(struct gen7_surface_state2), 32) */ 159 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7) 160 #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN7 /*MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) */ 161 162 #define BINDING_TABLE_ENTRIES 0xc0 163 #define LAST_BINDING_TABLE_ENTRIES 0x20 164 #define BINDING_TABLE_OFFSET(index) (/*ALIGN(sizeof(BINDING_TABLE_STATE),32)*/(sizeof(BINDING_TABLE_STATE)) * index) 165 166 #define SURFACE_STATE_SIZE (ALIGN(sizeof(SURFACE_STATE_G7),32)) 167 #define SURFACE_STATE_OFFSET(index) (BINDING_TABLE_OFFSET(BINDING_TABLE_ENTRIES)+(SURFACE_STATE_SIZE*index)) 168 #define BINDING_TABLE_SURFACE_SHIFT 5 169 170 171 #define MFX_SURFACE_PLANAR_420_8 4 172 #define MFX_SURFACE_PLANAR_411_8 5 173 #define MFX_SURFACE_PLANAR_422_8 6 174 175 176 #define HISTOGRAM_SIZE (136 * sizeof(unsigned int)) 177 178 #define MBPAK_HYBRID_STATE_P1 1 179 #define MBPAK_HYBRID_STATE_P2 2 180 181 #define CACHEABILITY_TYPE_NONE 0 182 #define CACHEABILITY_TYPE_LLC 1 183 #define CACHEABILITY_TYPE_L3 2 184 185 #define VDIRECTION_FULL_FRAME 2 186 187 #define MBENC_ILUMA_START_OFFSET 0 188 #define MBENC_ICHROMA_START_OFFSET 1 189 #define MBENC_P_START_OFFSET 2 190 #define MBENC_I_START_OFFSET 3 191 #define MBENC_IFRAME_DIST_OFFSET 4 192 193 #define MBPAK_PHASE1_OFFSET 1 194 #define MBPAK_PHASE2_OFFSET 0 195 196 #define BRC_INIT_OFFSET 0 197 #define BRC_RESET_OFFSET 1 198 199 #define BRC_UPDATE_OFFSET 0 200 201 #define KERNEL_DUMP_SIZE_VP8 (600000 * sizeof(DWORD)) 202 203 #define LAST_REF_FLAG_VP8 0x1 204 #define GOLDEN_REF_FLAG_VP8 0x2 205 #define ALT_REF_FLAG_VP8 0x4 206 207 #define NUM_BRC_IMG_STATE_READ_BUFFERS 3 208 #define NUM_BRC_CONSTANT_DATA_BUFFERS 3 209 210 #define BRC_CONSTANTSURFACE_WIDTH_G75 64 211 #define BRC_CONSTANTSURFACE_HEIGHT_G75 43 212 213 #define DEGREE_46 3 214 #endif 215