| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 63 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
121 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
122 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
201 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
202 priv->cru, VPLL0); in rk3308_mac_set_clk()
802 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
803 priv->cru, VPLL0); in rk3308_clk_get_rate()
|