/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 175 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues() local 176 (void)VReg0; in selectMergeValues() 177 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 178 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 206 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectUnmergeValues() local 207 (void)VReg0; in selectUnmergeValues() 208 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 209 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 211 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues() local 212 (void)VReg0; in selectMergeValues() 213 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 214 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 242 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectUnmergeValues() local 243 (void)VReg0; in selectUnmergeValues() 244 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 242 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 243 (void)VReg0; in selectMergeValues() 244 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 274 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 275 (void)VReg0; in selectUnmergeValues() 276 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 242 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 243 (void)VReg0; in selectMergeValues() 244 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 274 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 275 (void)VReg0; in selectUnmergeValues() 276 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 240 Register VReg0 = MIB.getReg(0); in selectMergeValues() local 241 (void)VReg0; in selectMergeValues() 242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 272 Register VReg0 = MIB.getReg(0); in selectUnmergeValues() local 273 (void)VReg0; in selectUnmergeValues() 274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 239 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues() local 240 (void)VReg0; in selectMergeValues() 241 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 242 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 271 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectUnmergeValues() local 272 (void)VReg0; in selectUnmergeValues() 273 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 274 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 242 Register VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues() local 243 (void)VReg0; in selectMergeValues() 244 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 274 Register VReg0 = MIB->getOperand(0).getReg(); in selectUnmergeValues() local 275 (void)VReg0; in selectUnmergeValues() 276 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 242 Register VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues() local 243 (void)VReg0; in selectMergeValues() 244 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 274 Register VReg0 = MIB->getOperand(0).getReg(); in selectUnmergeValues() local 275 (void)VReg0; in selectUnmergeValues() 276 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 242 Register VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues() local 243 (void)VReg0; in selectMergeValues() 244 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues() 245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues() 274 Register VReg0 = MIB->getOperand(0).getReg(); in selectUnmergeValues() local 275 (void)VReg0; in selectUnmergeValues() 276 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues() 277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
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