Home
last modified time | relevance | path

Searched refs:VgprBase (Results 1 – 25 of 30) sorted by relevance

12

/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp172 unsigned VgprBase = 0; in CheckNSA() local
215 VgprBase = PhysReg; in CheckNSA()
216 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp249 unsigned VgprBase = 0; in shrinkMIMG() local
257 VgprBase = Vgpr; in shrinkMIMG()
258 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
267 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp173 unsigned VgprBase = 0; in CheckNSA() local
216 VgprBase = PhysReg; in CheckNSA()
217 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp250 unsigned VgprBase = 0; in shrinkMIMG() local
258 VgprBase = Vgpr; in shrinkMIMG()
259 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
268 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
297 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp173 unsigned VgprBase = 0; in CheckNSA() local
216 VgprBase = PhysReg; in CheckNSA()
217 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp254 unsigned VgprBase = 0; in shrinkMIMG() local
262 VgprBase = Vgpr; in shrinkMIMG()
263 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
272 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
301 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp173 unsigned VgprBase = 0; in CheckNSA() local
216 VgprBase = PhysReg; in CheckNSA()
217 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp249 unsigned VgprBase = 0; in shrinkMIMG() local
257 VgprBase = Vgpr; in shrinkMIMG()
258 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
267 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0;
219 VgprBase = PhysReg; in hasSelfintersections()
220 else if (VgprBase + I != PhysReg)
H A DSIShrinkInstructions.cpp248 unsigned VgprBase = 0; in shrinkMIMG() local
256 VgprBase = Vgpr; in shrinkMIMG()
257 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
266 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
295 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
219 VgprBase = PhysReg; in CheckNSA()
220 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp248 unsigned VgprBase = 0; in shrinkMIMG() local
256 VgprBase = Vgpr; in shrinkMIMG()
257 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
266 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
295 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
211 VgprBase = PhysReg; in CheckNSA()
212 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp243 unsigned VgprBase = 0; in shrinkMIMG() local
251 VgprBase = Vgpr; in shrinkMIMG()
252 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
261 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
290 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp173 unsigned VgprBase = 0; in CheckNSA() local
216 VgprBase = PhysReg; in CheckNSA()
217 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp254 unsigned VgprBase = 0; in shrinkMIMG() local
262 VgprBase = Vgpr; in shrinkMIMG()
263 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
272 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
301 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
219 VgprBase = PhysReg; in CheckNSA()
220 else if (VgprBase + I != PhysReg) in CheckNSA()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp173 unsigned VgprBase = 0; in CheckNSA() local
216 VgprBase = PhysReg; in CheckNSA()
217 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp249 unsigned VgprBase = 0; in shrinkMIMG() local
257 VgprBase = Vgpr; in shrinkMIMG()
258 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
267 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
219 VgprBase = PhysReg; in CheckNSA()
220 else if (VgprBase + I != PhysReg) in CheckNSA()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
219 VgprBase = PhysReg; in CheckNSA()
220 else if (VgprBase + I != PhysReg) in CheckNSA()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp173 unsigned VgprBase = 0; in CheckNSA() local
216 VgprBase = PhysReg; in CheckNSA()
217 else if (VgprBase + I != PhysReg) in CheckNSA()
H A DSIShrinkInstructions.cpp249 unsigned VgprBase = 0; in shrinkMIMG() local
257 VgprBase = Vgpr; in shrinkMIMG()
258 } else if (VgprBase + i != Vgpr) in shrinkMIMG()
267 if (VgprBase + NewAddrDwords > 256) in shrinkMIMG()
296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
211 VgprBase = PhysReg; in CheckNSA()
212 else if (VgprBase + I != PhysReg) in CheckNSA()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp168 unsigned VgprBase = 0; in CheckNSA() local
219 VgprBase = PhysReg; in CheckNSA()
220 else if (VgprBase + I != PhysReg) in CheckNSA()

12