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/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_three_same.cpp31 const IR::U128 operand2 = v.ir.GetQ(Vm); in HighNarrowingOperation()
66 const IR::U128 operand2 = v.V(datasize, Vm); in SignedAbsoluteDifference()
482 const auto operand2 = V(datasize, Vm); in ADD_vector()
746 const IR::U128 rhs = V(datasize, Vm); in FCMEQ_reg_3()
769 const auto operand2 = V(datasize, Vm); in AND_asimd()
1018 const auto operand2 = V(datasize, Vm); in ORR_asimd_reg()
1029 const auto operand2 = V(datasize, Vm); in ORN_asimd()
1064 const auto operand2 = V(datasize, Vm); in SUB_2()
1113 const auto operand2 = V(datasize, Vm); in EOR_asimd()
1235 const auto operand3 = V(datasize, Vm); in BIT()
[all …]
H A Dsimd_three_different.cpp62 const auto p2 = v.Vpart(datasize, Vm, Q); in MultiplyLong()
113 const IR::U128 operand2 = get_operand(Vm); in LongOperation()
142 const IR::U128 tmp = v.Vpart(64, Vm, part); in WideOperation()
163 bool TranslatorVisitor::PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in PMULL() argument
172 const IR::U128 operand2 = Vpart(datasize, Vm, Q); in PMULL()
179 bool TranslatorVisitor::SABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SABAL() argument
183 bool TranslatorVisitor::SABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SABDL() argument
187 bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SADDL() argument
191 bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SADDW() argument
207 bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SSUBW() argument
[all …]
H A Dsimd_scalar_three_same.cpp39 const IR::U128 operand2 = v.V(64, Vm); in RoundingShiftLeft()
101 const IR::U128 operand2 = v.V(datasize, Vm); in ScalarFPCompareRegister()
132 const IR::UAny operand2 = V_scalar(esize, Vm); in SQADD_1()
147 const IR::UAny operand2 = V_scalar(esize, Vm); in SQDMULH_vec_1()
176 const IR::UAny operand2 = V_scalar(esize, Vm); in SQSUB_1()
187 const IR::UAny operand2 = V_scalar(esize, Vm); in UQADD_1()
265 const IR::U128 operand2 = V(64, Vm); in CMTST_1()
299 const IR::U16 operand2 = V_scalar(esize, Vm); in FRECPS_1()
349 const IR::U128 rhs = V(128, Vm); in FCMEQ_reg_1()
389 const IR::U128 operand2 = V(64, Vm); in SSHL_1()
[all …]
H A Dimpl.h431 bool SHA1C(Vec Vm, Vec Vn, Vec Vd);
432 bool SHA1P(Vec Vm, Vec Vn, Vec Vd);
433 bool SHA1M(Vec Vm, Vec Vn, Vec Vd);
434 bool SHA1SU0(Vec Vm, Vec Vn, Vec Vd);
435 bool SHA256H(Vec Vm, Vec Vn, Vec Vd);
436 bool SHA256H2(Vec Vm, Vec Vn, Vec Vd);
450 bool FRECPS_1(Vec Vm, Vec Vn, Vec Vd);
456 bool FACGE_1(Vec Vm, Vec Vn, Vec Vd);
458 bool FABD_1(Vec Vm, Vec Vn, Vec Vd);
462 bool FACGT_1(Vec Vm, Vec Vn, Vec Vd);
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_three_same.cpp31 const IR::U128 operand2 = v.ir.GetQ(Vm); in HighNarrowingOperation()
66 const IR::U128 operand2 = v.V(datasize, Vm); in SignedAbsoluteDifference()
482 const auto operand2 = V(datasize, Vm); in ADD_vector()
746 const IR::U128 rhs = V(datasize, Vm); in FCMEQ_reg_3()
769 const auto operand2 = V(datasize, Vm); in AND_asimd()
1018 const auto operand2 = V(datasize, Vm); in ORR_asimd_reg()
1029 const auto operand2 = V(datasize, Vm); in ORN_asimd()
1064 const auto operand2 = V(datasize, Vm); in SUB_2()
1113 const auto operand2 = V(datasize, Vm); in EOR_asimd()
1235 const auto operand3 = V(datasize, Vm); in BIT()
[all …]
H A Dsimd_three_different.cpp62 const auto p2 = v.Vpart(datasize, Vm, Q); in MultiplyLong()
113 const IR::U128 operand2 = get_operand(Vm); in LongOperation()
142 const IR::U128 tmp = v.Vpart(64, Vm, part); in WideOperation()
163 bool TranslatorVisitor::PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in PMULL() argument
172 const IR::U128 operand2 = Vpart(datasize, Vm, Q); in PMULL()
179 bool TranslatorVisitor::SABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SABAL() argument
183 bool TranslatorVisitor::SABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SABDL() argument
187 bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SADDL() argument
191 bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SADDW() argument
207 bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SSUBW() argument
[all …]
H A Dsimd_scalar_three_same.cpp39 const IR::U128 operand2 = v.V(64, Vm); in RoundingShiftLeft()
101 const IR::U128 operand2 = v.V(datasize, Vm); in ScalarFPCompareRegister()
132 const IR::UAny operand2 = V_scalar(esize, Vm); in SQADD_1()
147 const IR::UAny operand2 = V_scalar(esize, Vm); in SQDMULH_vec_1()
176 const IR::UAny operand2 = V_scalar(esize, Vm); in SQSUB_1()
187 const IR::UAny operand2 = V_scalar(esize, Vm); in UQADD_1()
265 const IR::U128 operand2 = V(64, Vm); in CMTST_1()
299 const IR::U16 operand2 = V_scalar(esize, Vm); in FRECPS_1()
349 const IR::U128 rhs = V(128, Vm); in FCMEQ_reg_1()
389 const IR::U128 operand2 = V(64, Vm); in SSHL_1()
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_three_same.cpp31 const IR::U128 operand2 = v.ir.GetQ(Vm); in HighNarrowingOperation()
66 const IR::U128 operand2 = v.V(datasize, Vm); in SignedAbsoluteDifference()
482 const auto operand2 = V(datasize, Vm); in ADD_vector()
746 const IR::U128 rhs = V(datasize, Vm); in FCMEQ_reg_3()
769 const auto operand2 = V(datasize, Vm); in AND_asimd()
1018 const auto operand2 = V(datasize, Vm); in ORR_asimd_reg()
1029 const auto operand2 = V(datasize, Vm); in ORN_asimd()
1064 const auto operand2 = V(datasize, Vm); in SUB_2()
1113 const auto operand2 = V(datasize, Vm); in EOR_asimd()
1235 const auto operand3 = V(datasize, Vm); in BIT()
[all …]
H A Dsimd_three_different.cpp62 const auto p2 = v.Vpart(datasize, Vm, Q); in MultiplyLong()
113 const IR::U128 operand2 = get_operand(Vm); in LongOperation()
142 const IR::U128 tmp = v.Vpart(64, Vm, part); in WideOperation()
163 bool TranslatorVisitor::PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in PMULL() argument
172 const IR::U128 operand2 = Vpart(datasize, Vm, Q); in PMULL()
179 bool TranslatorVisitor::SABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SABAL() argument
183 bool TranslatorVisitor::SABDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SABDL() argument
187 bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SADDL() argument
191 bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SADDW() argument
207 bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in SSUBW() argument
[all …]
H A Dsimd_scalar_three_same.cpp39 const IR::U128 operand2 = v.V(64, Vm); in RoundingShiftLeft()
101 const IR::U128 operand2 = v.V(datasize, Vm); in ScalarFPCompareRegister()
132 const IR::UAny operand2 = V_scalar(esize, Vm); in SQADD_1()
147 const IR::UAny operand2 = V_scalar(esize, Vm); in SQDMULH_vec_1()
176 const IR::UAny operand2 = V_scalar(esize, Vm); in SQSUB_1()
187 const IR::UAny operand2 = V_scalar(esize, Vm); in UQADD_1()
265 const IR::U128 operand2 = V(64, Vm); in CMTST_1()
299 const IR::U16 operand2 = V_scalar(esize, Vm); in FRECPS_1()
349 const IR::U128 rhs = V(128, Vm); in FCMEQ_reg_1()
389 const IR::U128 operand2 = V(64, Vm); in SSHL_1()
[all …]
H A Dimpl.h431 bool SHA1C(Vec Vm, Vec Vn, Vec Vd);
432 bool SHA1P(Vec Vm, Vec Vn, Vec Vd);
433 bool SHA1M(Vec Vm, Vec Vn, Vec Vd);
434 bool SHA1SU0(Vec Vm, Vec Vn, Vec Vd);
435 bool SHA256H(Vec Vm, Vec Vn, Vec Vd);
436 bool SHA256H2(Vec Vm, Vec Vn, Vec Vd);
450 bool FRECPS_1(Vec Vm, Vec Vn, Vec Vd);
456 bool FACGE_1(Vec Vm, Vec Vn, Vec Vd);
458 bool FABD_1(Vec Vm, Vec Vn, Vec Vd);
462 bool FACGT_1(Vec Vm, Vec Vn, Vec Vd);
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dasimd_two_regs_misc.cpp32 const auto m = ToVector(Q, Vm, M); in CompareWithZero()
87 const auto m = ToVector(Q, Vm, M); in PairedAddOperation()
118 const auto m = ToVector(Q, Vm, M); in asimd_VREV()
240 const auto m = ToVector(Q, Vm, M); in asimd_VCLS()
264 const auto m = ToVector(Q, Vm, M); in asimd_VCLZ()
286 const auto m = ToVector(Q, Vm, M); in asimd_VCNT()
304 const auto m = ToVector(Q, Vm, M); in asimd_VMVN_reg()
328 const auto m = ToVector(Q, Vm, M); in asimd_VQABS()
348 const auto m = ToVector(Q, Vm, M); in asimd_VQNEG()
387 const auto m = ToVector(Q, Vm, M); in asimd_VABS()
[all …]
H A Dasimd_three_regs.cpp37 const auto m = ToVector(Q, Vm, M); in BitwiseInstruction()
67 const auto m = ToVector(Q, Vm, M); in FloatingPointInstruction()
91 const auto m = ToVector(Q, Vm, M); in IntegerComparison()
126 const auto m = ToVector(Q, Vm, M); in FloatComparison()
164 const auto m = ToVector(Q, Vm, M); in AbsoluteDifference()
263 const auto m = ToVector(Q, Vm, M); in asimd_VHADD()
285 const auto m = ToVector(Q, Vm, M); in asimd_VQADD()
307 const auto m = ToVector(Q, Vm, M); in asimd_VRHADD()
377 const auto m = ToVector(Q, Vm, M); in asimd_VHSUB()
399 const auto m = ToVector(Q, Vm, M); in asimd_VQSUB()
[all …]
H A Dasimd_two_regs_shift.cpp66 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in ShiftRight()
72 const auto m = ToVector(Q, Vm, M); in ShiftRight()
98 if (Common::Bit<0>(Vm)) { in ShiftRightNarrowing()
107 const auto m = ToVector(true, Vm, M); in ShiftRightNarrowing()
144 return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm, in asimd_SHR()
176 const auto m = ToVector(Q, Vm, M); in asimd_VSRI()
202 const auto m = ToVector(Q, Vm, M); in asimd_VSLI()
229 const auto m = ToVector(Q, Vm, M); in asimd_VQSHL()
264 const auto m = ToVector(Q, Vm, M); in asimd_VSHL()
315 const auto m = ToVector(false, Vm, M); in asimd_VSHLL()
[all …]
H A Dtranslate_arm.h405 bool vfp_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
407 bool vfp_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
408 bool vfp_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm);
535 bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
547 bool v8_AESD(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
548 bool v8_AESE(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
549 bool v8_AESIMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
550 bool v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
565 bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);
569 bool asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
[all …]
/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/Common/
H A DArmEmitter.h348 u32 EncodeVm(ARMReg Vm);
624 void VCMP(ARMReg Vd, ARMReg Vm);
625 void VCMPE(ARMReg Vd, ARMReg Vm);
634 void VSQRT(ARMReg Vd, ARMReg Vm);
639 void VABS(ARMReg Vd, ARMReg Vm);
640 void VNEG(ARMReg Vd, ARMReg Vm);
659 void VABS(u32 Size, ARMReg Vd, ARMReg Vm);
672 void VCEQ(u32 Size, ARMReg Vd, ARMReg Vm);
674 void VCGE(u32 Size, ARMReg Vd, ARMReg Vm);
747 void VMVN(ARMReg Vd, ARMReg Vm);
[all …]
H A DArmEmitter.cpp1265 Vm = SubBase(Vm); in VABD()
1269 | ((Vm & 0x10) << 2) | (Vm & 0xF)); in VABD()
1281 Vm = SubBase(Vm); in VADD()
1285 | ((Vm & 0x10) << 1) | (Vm & 0xF)); in VADD()
1296 Vm = SubBase(Vm); in VSUB()
1300 | ((Vm & 0x10) << 2) | (Vm & 0xF)); in VSUB()
1939 VACGE(Vd, Vm, Vn); in VACLE()
2648 Vm = SubBase(Vm); in VRSQRTE()
2652 | ((Vm & 0x10) << 1) | (Vm & 0xF)); in VRSQRTE()
3154 Vm = SubBase(Vm); in VREVX()
[all …]
/dports/emulators/ppsspp/ppsspp-1.12.3/Common/
H A DArmEmitter.h348 u32 EncodeVm(ARMReg Vm);
624 void VCMP(ARMReg Vd, ARMReg Vm);
625 void VCMPE(ARMReg Vd, ARMReg Vm);
634 void VSQRT(ARMReg Vd, ARMReg Vm);
639 void VABS(ARMReg Vd, ARMReg Vm);
640 void VNEG(ARMReg Vd, ARMReg Vm);
659 void VABS(u32 Size, ARMReg Vd, ARMReg Vm);
672 void VCEQ(u32 Size, ARMReg Vd, ARMReg Vm);
674 void VCGE(u32 Size, ARMReg Vd, ARMReg Vm);
747 void VMVN(ARMReg Vd, ARMReg Vm);
[all …]
H A DArmEmitter.cpp1265 Vm = SubBase(Vm); in VABD()
1269 | ((Vm & 0x10) << 2) | (Vm & 0xF)); in VABD()
1281 Vm = SubBase(Vm); in VADD()
1285 | ((Vm & 0x10) << 1) | (Vm & 0xF)); in VADD()
1296 Vm = SubBase(Vm); in VSUB()
1300 | ((Vm & 0x10) << 2) | (Vm & 0xF)); in VSUB()
1939 VACGE(Vd, Vm, Vn); in VACLE()
2648 Vm = SubBase(Vm); in VRSQRTE()
2652 | ((Vm & 0x10) << 1) | (Vm & 0xF)); in VRSQRTE()
3154 Vm = SubBase(Vm); in VREVX()
[all …]
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/Common/
H A DArmEmitter.h348 u32 EncodeVm(ARMReg Vm);
624 void VCMP(ARMReg Vd, ARMReg Vm);
625 void VCMPE(ARMReg Vd, ARMReg Vm);
634 void VSQRT(ARMReg Vd, ARMReg Vm);
639 void VABS(ARMReg Vd, ARMReg Vm);
640 void VNEG(ARMReg Vd, ARMReg Vm);
659 void VABS(u32 Size, ARMReg Vd, ARMReg Vm);
672 void VCEQ(u32 Size, ARMReg Vd, ARMReg Vm);
674 void VCGE(u32 Size, ARMReg Vd, ARMReg Vm);
747 void VMVN(ARMReg Vd, ARMReg Vm);
[all …]
H A DArmEmitter.cpp1265 Vm = SubBase(Vm); in VABD()
1269 | ((Vm & 0x10) << 2) | (Vm & 0xF)); in VABD()
1281 Vm = SubBase(Vm); in VADD()
1285 | ((Vm & 0x10) << 1) | (Vm & 0xF)); in VADD()
1296 Vm = SubBase(Vm); in VSUB()
1300 | ((Vm & 0x10) << 2) | (Vm & 0xF)); in VSUB()
1939 VACGE(Vd, Vm, Vn); in VACLE()
2648 Vm = SubBase(Vm); in VRSQRTE()
2652 | ((Vm & 0x10) << 1) | (Vm & 0xF)); in VRSQRTE()
3154 Vm = SubBase(Vm); in VREVX()
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dasimd_three_same.cpp14 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in BitwiseInstruction()
19 const auto m = ToVector(Q, Vm, M); in BitwiseInstruction()
40 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VHADD()
50 const auto m = ToVector(Q, Vm, M); in asimd_VHADD()
62 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VQADD()
72 const auto m = ToVector(Q, Vm, M); in asimd_VQADD()
84 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VRHADD()
94 const auto m = ToVector(Q, Vm, M); in asimd_VRHADD()
154 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VHSUB()
164 const auto m = ToVector(Q, Vm, M); in asimd_VHSUB()
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dasimd_three_same.cpp14 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in BitwiseInstruction()
19 const auto m = ToVector(Q, Vm, M); in BitwiseInstruction()
40 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VHADD()
50 const auto m = ToVector(Q, Vm, M); in asimd_VHADD()
62 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VQADD()
72 const auto m = ToVector(Q, Vm, M); in asimd_VQADD()
84 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VRHADD()
94 const auto m = ToVector(Q, Vm, M); in asimd_VRHADD()
154 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { in asimd_VHSUB()
164 const auto m = ToVector(Q, Vm, M); in asimd_VHSUB()
[all …]
/dports/lang/rust/rustc-1.58.1-src/library/stdarch/crates/intrinsic-test/acle/tools/intrinsic_db/
H A Dadvsimd.csv17 int8x8_t vadd_s8(int8x8_t a, int8x8_t b) a -> Vn.8B;b -> Vm.8B ADD Vd.8B,Vn.8B,Vm.8B Vd.8B -> resul…
19 int16x4_t vadd_s16(int16x4_t a, int16x4_t b) a -> Vn.4H;b -> Vm.4H ADD Vd.4H,Vn.4H,Vm.4H Vd.4H -> r…
20 int16x8_t vaddq_s16(int16x8_t a, int16x8q_t b) a -> Vn.8H;b -> Vm.8H ADD Vd.8H,Vn.8H,Vm.8H Vd.8H ->…
21 int32x2_t vadd_s32(int32x2_t a, int32x2_t b) a -> Vn.2S;b -> Vm.2S ADD Vd.2S,Vn.2S,Vm.2S Vd.2S -> r…
22 int32x4_t vaddq_s32(int32x4_t a, int32x4_t b) a -> Vn.4S;b -> Vm.4S ADD Vd.4S,Vn.4S,Vm.4S Vd.4S -> …
24 int64x2_t vaddq_s64(int64x2_t a, int64x2_t b) a -> Vn.2D;b -> Vm.2D ADD Vd.2D,Vn.2D,Vm.2D Vd.2D -> …
25 uint8x8_t vadd_u8(uint8x8_t a, uint8x8_t b) a -> Vn.8B;b -> Vm.8B ADD Vd.8B,Vn.8B,Vm.8B Vd.8B -> re…
2881 int32_t vaddv_s32(int32x2_t a) a -> Vn.2S;a -> Vm.2S ADDP Vd.2S,Vn.2S,Vm.2S Vd.S[0] -> result A64
2888 uint32_t vaddv_u32(uint32x2_t a) a -> Vn.2S;a -> Vm.2S ADDP Vd.2S,Vn.2S,Vm.2S Vd.S[0] -> result A64
2910 int32_t vmaxv_s32(int32x2_t a) a -> Vn.2S;a -> Vm.2S SMAXP Vd.2S,Vn.2S,Vm.2S Vd.S[0] -> result A64
[all …]
/dports/lang/rust/rustc-1.58.1-src/library/stdarch/crates/intrinsic-test/acle/neon_intrinsics/
H A Dadvsimd.rst15045 | int8x8_t low, | high -> Vm.8B | INS Vd.D[1],Vm.D[0] | …
15051 | int16x4_t low, | high -> Vm.4H | INS Vd.D[1],Vm.D[0] | …
15057 | int32x2_t low, | high -> Vm.2S | INS Vd.D[1],Vm.D[0] | …
15063 | int64x1_t low, | high -> Vm.1D | INS Vd.D[1],Vm.D[0] | …
15069 | uint8x8_t low, | high -> Vm.8B | INS Vd.D[1],Vm.D[0] | …
15075 | uint16x4_t low, | high -> Vm.4H | INS Vd.D[1],Vm.D[0] | …
15081 | uint32x2_t low, | high -> Vm.2S | INS Vd.D[1],Vm.D[0] | …
15087 | uint64x1_t low, | high -> Vm.1D | INS Vd.D[1],Vm.D[0] | …
15093 | poly64x1_t low, | high -> Vm.1D | INS Vd.D[1],Vm.D[0] | …
15099 | float16x4_t low, | high -> Vm.4H | INS Vd.D[1],Vm.D[0] | …
[all …]

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