/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
H A D | axi_round.v | 8 #(parameter WIDTH_IN=17, constant 15 input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 21 if (WIDTH_IN == WIDTH_OUT) begin 28 wire [WIDTH_IN-WIDTH_OUT-1:0] err; 31 assign round_corr_rtz = (i_tdata[WIDTH_IN-1] & |i_tdata[WIDTH_IN-WIDTH_OUT-1:0]); 32 assign round_corr_nearest = i_tdata[WIDTH_IN-WIDTH_OUT-1]; 34 assign round_corr_nearest_safe = (WIDTH_IN-WIDTH_OUT > 1) ? 35 … ((~i_tdata[WIDTH_IN-1] & (&i_tdata[WIDTH_IN-2:WIDTH_IN-WIDTH_OUT])) ? 1'b0 : round_corr_nearest) : 43 assign out = i_tdata[WIDTH_IN-1:WIDTH_IN-WIDTH_OUT] + round_corr; 45 assign err = i_tdata - {out,{(WIDTH_IN-WIDTH_OUT){1'b0}}};
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H A D | axi_packer.v | 8 parameter WIDTH_IN = 8, // Input bit width constant 13 input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 17 localparam M = WIDTH_OUT/WIDTH_IN; 46 packed_tdata[WIDTH_OUT-1:WIDTH_OUT-WIDTH_IN] <= i_tdata; 48 …packed_tdata[WIDTH_OUT-(i+1)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[WIDTH_OUT-i*WIDTH_IN-1 -: WID… 51 packed_tdata[WIDTH_IN-1:0] <= i_tdata; 53 … packed_tdata[(i+2)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[(i+1)*WIDTH_IN-1 -: WIDTH_IN];
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H A D | axi_clip_complex.v | 8 parameter WIDTH_IN = 24, constant 13 input [2*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 17 wire [WIDTH_IN-1:0] ii_tdata, iq_tdata; 23 split_complex #(.WIDTH(WIDTH_IN)) split_complex ( 28 axi_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_clip_i ( 33 axi_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_clip_q (
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H A D | axi_round_and_clip_complex.v | 9 #(parameter WIDTH_IN=24, constant 14 input [2*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 17 wire [WIDTH_IN-1:0] ii_tdata, iq_tdata; 23 split_complex #(.WIDTH(WIDTH_IN)) split 28 …axi_round_and_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .CLIP_BITS(CLIP_BITS), .FIFOSIZE(… 33 …axi_round_and_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .CLIP_BITS(CLIP_BITS), .FIFOSIZE(…
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H A D | axi_round_complex.v | 8 parameter WIDTH_IN = 24, constant 13 input [2*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 17 wire [WIDTH_IN-1:0] ii_tdata, iq_tdata; 23 split_complex #(.WIDTH(WIDTH_IN)) split_complex ( 28 axi_round #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_round_i ( 33 axi_round #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_round_q (
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H A D | axi_clip.v | 8 #(parameter WIDTH_IN=24, constant 12 input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 16 if (WIDTH_IN == WIDTH_OUT) begin 22 wire overflow = |i_tdata[WIDTH_IN-1:WIDTH_OUT-1] & ~(&i_tdata[WIDTH_IN-1:WIDTH_OUT-1]); 24 (i_tdata[WIDTH_IN-1] ? {1'b1,{(WIDTH_OUT-1){1'b0}}} : {1'b0,{(WIDTH_OUT-1){1'b1}}}) :
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H A D | axi_round_and_clip.v | 24 parameter WIDTH_IN=24, constant 30 input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 38 if (WIDTH_IN == WIDTH_OUT+CLIP_BITS) begin 45 .WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT+CLIP_BITS), 60 .WIDTH_IN(WIDTH_OUT+CLIP_BITS), .WIDTH_OUT(WIDTH_OUT),
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H A D | axi_bit_reduce.v | 10 #(parameter WIDTH_IN=48, constant 14 (input [VECTOR_WIDTH*WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 20 … o_tdata[(i+1)*WIDTH_OUT-1:i*WIDTH_OUT] = i_tdata[(i+1)*WIDTH_IN-DROP_TOP-1:i*WIDTH_IN+(WIDTH_IN-W…
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H A D | axi_clip_unsigned.v | 7 #(parameter WIDTH_IN=24, constant 11 input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 14 wire overflow = |i_tdata[WIDTH_IN-1:WIDTH_OUT];
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H A D | phase_accum.v | 12 parameter WIDTH_IN = 16, constant 16 input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, 63 .WIDTH_IN(WIDTH_ACCUM),
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H A D | multiply.v | 104 .WIDTH_IN(WIDTH_A+WIDTH_B), 113 .WIDTH_IN(WIDTH_A+WIDTH_B-DROP_TOP_P), 122 .WIDTH_IN(WIDTH_A+WIDTH_B),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/ |
H A D | round_sd.v | 9 parameter WIDTH_IN=18, constant 14 input [WIDTH_IN-1:0] in, input strobe_in, 18 localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; 21 wire [WIDTH_IN-1:0] err_ext, sum; 25 sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext)); 27 add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg ( 28 ….clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : {WIDTH_IN{1'b0}}), .strobe_in… 30 round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out_pre), .err(err));
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H A D | small_hb_dec.v | 32 round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in 126 round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
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H A D | tx_frontend.v | 87 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i 90 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
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H A D | ddc_chain.v | 286 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i 288 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q 363 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i 365 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q
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H A D | rx_dcoffset.v | 44 round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/ |
H A D | round_sd.v | 4 #(parameter WIDTH_IN=18, constant 8 input [WIDTH_IN-1:0] in, input strobe_in, 11 localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; 14 wire [WIDTH_IN-1:0] err_ext, sum; 16 sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext)); 18 add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg 21 round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
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H A D | round_sd_tb.v | 14 localparam WIDTH_IN = 8; constant 17 reg [WIDTH_IN-1:0] adc_in, adc_in_del; 20 integer factor = 1<<(WIDTH_IN-WIDTH_OUT); 25 if(adc_in_del[WIDTH_IN-1]) 39 round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT))
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H A D | small_hb_dec.v | 39 round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in 128 round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
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H A D | tx_frontend.v | 86 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i 89 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
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H A D | rx_dcoffset.v | 52 round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
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H A D | ddc_chain.v | 178 round_sd #(.WIDTH_IN(34),.WIDTH_OUT(16)) round_i 181 round_sd #(.WIDTH_IN(34),.WIDTH_OUT(16)) round_q
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/ |
H A D | tx_frontend_gen3.v | 139 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i ( 141 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
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H A D | rx_frontend_gen3.v | 254 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i ( 256 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/ |
H A D | rfnoc_moving_avg_core.v | 275 .WIDTH_IN (47), 292 .WIDTH_IN (47),
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