/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
H A D | axi_round.v | 9 parameter WIDTH_OUT=16, constant 16 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); 18 wire [WIDTH_OUT-1:0] out; 21 if (WIDTH_IN == WIDTH_OUT) begin 28 wire [WIDTH_IN-WIDTH_OUT-1:0] err; 31 assign round_corr_rtz = (i_tdata[WIDTH_IN-1] & |i_tdata[WIDTH_IN-WIDTH_OUT-1:0]); 32 assign round_corr_nearest = i_tdata[WIDTH_IN-WIDTH_OUT-1]; 34 assign round_corr_nearest_safe = (WIDTH_IN-WIDTH_OUT > 1) ? 43 assign out = i_tdata[WIDTH_IN-1:WIDTH_IN-WIDTH_OUT] + round_corr; 45 assign err = i_tdata - {out,{(WIDTH_IN-WIDTH_OUT){1'b0}}}; [all …]
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H A D | axi_clip.v | 9 parameter WIDTH_OUT=16, constant 13 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); 16 if (WIDTH_IN == WIDTH_OUT) begin 22 wire overflow = |i_tdata[WIDTH_IN-1:WIDTH_OUT-1] & ~(&i_tdata[WIDTH_IN-1:WIDTH_OUT-1]); 23 wire [WIDTH_OUT-1:0] out = overflow ? 24 (i_tdata[WIDTH_IN-1] ? {1'b1,{(WIDTH_OUT-1){1'b0}}} : {1'b0,{(WIDTH_OUT-1){1'b1}}}) : 25 i_tdata[WIDTH_OUT-1:0]; 27 axi_fifo #(.WIDTH(WIDTH_OUT+1), .SIZE(FIFOSIZE)) flop
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H A D | axi_round_and_clip.v | 25 parameter WIDTH_OUT=16, constant 31 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready 34 wire [WIDTH_OUT+CLIP_BITS-1:0] int_tdata; 38 if (WIDTH_IN == WIDTH_OUT+CLIP_BITS) begin 45 .WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT+CLIP_BITS), 60 .WIDTH_IN(WIDTH_OUT+CLIP_BITS), .WIDTH_OUT(WIDTH_OUT),
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H A D | axi_packer.v | 9 parameter WIDTH_OUT = 32, // Output bit width constant 14 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready 17 localparam M = WIDTH_OUT/WIDTH_IN; 20 reg [WIDTH_OUT-1:0] packed_tdata; 46 packed_tdata[WIDTH_OUT-1:WIDTH_OUT-WIDTH_IN] <= i_tdata; 48 …packed_tdata[WIDTH_OUT-(i+1)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[WIDTH_OUT-i*WIDTH_IN-1 -: WID… 60 axi_fifo_flop #(.WIDTH(WIDTH_OUT+1)) axi_fifo_flop_pack (
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H A D | axi_clip_unsigned.v | 8 parameter WIDTH_OUT=16, constant 12 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); 14 wire overflow = |i_tdata[WIDTH_IN-1:WIDTH_OUT]; 16 wire [WIDTH_OUT-1:0] out = overflow ? {1'b0,{(WIDTH_OUT-1){1'b1}}} : i_tdata[WIDTH_OUT-1:0]; 18 axi_fifo #(.WIDTH(WIDTH_OUT+1), .SIZE(FIFOSIZE)) flop
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H A D | axi_clip_complex.v | 9 parameter WIDTH_OUT = 16, constant 14 output [2*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready 20 wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata; 28 axi_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_clip_i ( 33 axi_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_clip_q ( 38 join_complex #(.WIDTH(WIDTH_OUT)) join_complex (
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H A D | axi_round_and_clip_complex.v | 10 parameter WIDTH_OUT=16, constant 15 output [2*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); 20 wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata; 28 …axi_round_and_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .CLIP_BITS(CLIP_BITS), .FIFOSIZE(… 33 …axi_round_and_clip #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .CLIP_BITS(CLIP_BITS), .FIFOSIZE(… 38 join_complex #(.WIDTH(WIDTH_OUT)) join_complex
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H A D | axi_round_complex.v | 9 parameter WIDTH_OUT = 16, constant 14 output [2*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready 20 wire [WIDTH_OUT-1:0] oi_tdata, oq_tdata; 28 axi_round #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_round_i ( 33 axi_round #(.WIDTH_IN(WIDTH_IN), .WIDTH_OUT(WIDTH_OUT), .FIFOSIZE(FIFOSIZE)) axi_round_q ( 38 join_complex #(.WIDTH(WIDTH_OUT)) join_complex (
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H A D | axi_bit_reduce.v | 11 parameter WIDTH_OUT=25, constant 15 output [VECTOR_WIDTH*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); 20 …assign o_tdata[(i+1)*WIDTH_OUT-1:i*WIDTH_OUT] = i_tdata[(i+1)*WIDTH_IN-DROP_TOP-1:i*WIDTH_IN+(WIDT…
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H A D | phase_accum.v | 13 parameter WIDTH_OUT = 16) constant 17 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready 25 wire [WIDTH_OUT-1:0] output_round_tdata; 56 if (WIDTH_ACCUM == WIDTH_OUT) begin 64 .WIDTH_OUT(WIDTH_OUT))
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H A D | multiply.v | 105 .WIDTH_OUT(WIDTH_P), 114 .WIDTH_OUT(WIDTH_P)) 123 .WIDTH_OUT(WIDTH_A+WIDTH_B-DROP_TOP_P),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/ |
H A D | round_sd_tb.v | 15 localparam WIDTH_OUT = 5; constant 18 wire [WIDTH_OUT-1:0] adc_out; 20 integer factor = 1<<(WIDTH_IN-WIDTH_OUT); 29 if(adc_out[WIDTH_OUT-1]) 39 round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT))
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H A D | tx_frontend.v | 4 parameter WIDTH_OUT=16, constant 9 output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b 15 wire [WIDTH_OUT-1:0] i_final, q_final; 86 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i 89 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
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H A D | round_sd.v | 5 parameter WIDTH_OUT=16, constant 9 output [WIDTH_OUT-1:0] out, output strobe_out); 11 localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; 21 round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
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H A D | small_hb_dec.v | 39 round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in 128 round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
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H A D | rx_dcoffset.v | 52 round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
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H A D | ddc_chain.v | 178 round_sd #(.WIDTH_IN(34),.WIDTH_OUT(16)) round_i 181 round_sd #(.WIDTH_IN(34),.WIDTH_OUT(16)) round_q
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/ |
H A D | tx_frontend.v | 9 parameter WIDTH_OUT=16, constant 14 output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b 20 wire [WIDTH_OUT-1:0] i_final, q_final; 87 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i 90 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
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H A D | round_sd.v | 10 parameter WIDTH_OUT=16, constant 15 output reg [WIDTH_OUT-1:0] out, output reg strobe_out 18 localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; 22 wire [WIDTH_OUT-1:0] out_pre; 30 round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out_pre), .err(err));
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H A D | small_hb_dec.v | 32 round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in 126 round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
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H A D | ddc_chain.v | 286 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i 288 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q 363 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i 365 round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q
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H A D | rx_dcoffset.v | 44 round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/ |
H A D | tx_frontend_gen3.v | 139 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i ( 141 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
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H A D | rx_frontend_gen3.v | 254 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i ( 256 round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/ |
H A D | rfnoc_moving_avg_core.v | 276 .WIDTH_OUT (16), 293 .WIDTH_OUT (16),
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