/dports/emulators/mess/mame-mame0226/src/devices/cpu/sparc/ |
H A D | sparcdefs.h | 375 #define WRPSR (OP3 == OP3_WRPSR) macro
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H A D | sparc.cpp | 1205 if (((WRPSR || WRWIM || WRTBR) || (WRASR && m_privileged_asr[RS1])) && IS_USER) in execute_rdsr() 1331 else if (WRPSR) in execute_wrsr()
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/sparc/ |
H A D | sparcdefs.h | 375 #define WRPSR (OP3 == OP3_WRPSR) macro
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H A D | sparc.cpp | 1205 if (((WRPSR || WRWIM || WRTBR) || (WRASR && m_privileged_asr[RS1])) && IS_USER) in execute_rdsr() 1331 else if (WRPSR) in execute_wrsr()
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/dports/devel/avr-gdb/gdb-7.3.1/sim/erc32/ |
H A D | exec.c | 175 #define WRPSR 0x31 macro 1072 case WRPSR:
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/dports/devel/gdb761/gdb-7.6.1/sim/erc32/ |
H A D | exec.c | 175 #define WRPSR 0x31 macro 1072 case WRPSR:
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/erc32/ |
H A D | exec.c | 175 #define WRPSR 0x31 macro 1072 case WRPSR:
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/erc32/ |
H A D | exec.c | 175 #define WRPSR 0x31 macro 1072 case WRPSR:
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1605 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1605 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1592 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1605 // The partial write WRPSR instruction has a non-zero destination
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1605 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1605 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1592 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1605 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1573 // The partial write WRPSR instruction has a non-zero destination
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Sparc/ |
H A D | SparcInstrInfo.td | 1574 // The partial write WRPSR instruction has a non-zero destination
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/dports/games/libretro-paralleln64/parallel-n64-6e26fbb/mupen64plus-rsp-paraLLEl/lightning/lib/ |
H A D | jit_sparc-cpu.c | 530 # define WRPSR(rs1, rs2, rd) f3r(2, rd, 49, rs1, rs2) macro
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