/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/ |
H A D | tx_packer.v | 83 reg WR_2; register 95 WR_2 <= 0; 97 WR_2 <= WR_1; 104 WR_tx <= WR_1 & ~WR_2;
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | mips16-opc.c | 147 #define WR_2 INSN_WRITE_2 macro 153 #define MOD_2 (WR_2|RD_2)
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H A D | micromips-opc.c | 211 #define WR_2 INSN_WRITE_2 macro 217 #define MOD_2 (WR_2|RD_2) 625 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 626 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 869 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 870 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 874 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, 875 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
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H A D | mips-opc.c | 230 #define WR_2 INSN_WRITE_2 macro 236 #define MOD_2 (WR_2|RD_2) 494 {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 }, 496 {"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 }, 1078 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1079 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1488 {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1489 {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1490 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, 1491 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | mips16-opc.c | 147 #define WR_2 INSN_WRITE_2 macro 153 #define MOD_2 (WR_2|RD_2)
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H A D | micromips-opc.c | 211 #define WR_2 INSN_WRITE_2 macro 217 #define MOD_2 (WR_2|RD_2) 625 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 626 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 869 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 870 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 874 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, 875 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
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H A D | mips-opc.c | 230 #define WR_2 INSN_WRITE_2 macro 236 #define MOD_2 (WR_2|RD_2) 494 {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 }, 496 {"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 }, 1078 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1079 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1488 {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1489 {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1490 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, 1491 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, [all …]
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | mips16-opc.c | 166 #define WR_2 INSN_WRITE_2 macro 172 #define MOD_2 (WR_2|RD_2)
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H A D | mips-opc.c | 233 #define WR_2 INSN_WRITE_2 macro 240 #define MOD_2 (WR_2|RD_2) 522 {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, 1111 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1303 {"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, 1305 {"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, 1523 {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1524 {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1525 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, 1526 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, [all …]
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H A D | micromips-opc.c | 212 #define WR_2 INSN_WRITE_2 macro 218 #define MOD_2 (WR_2|RD_2) 637 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 638 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 888 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 889 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 897 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, 898 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | mips16-opc.c | 166 #define WR_2 INSN_WRITE_2 macro 172 #define MOD_2 (WR_2|RD_2)
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H A D | mips-opc.c | 233 #define WR_2 INSN_WRITE_2 macro 240 #define MOD_2 (WR_2|RD_2) 522 {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, 1111 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1303 {"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, 1305 {"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, 1523 {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1524 {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1525 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, 1526 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, [all …]
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H A D | micromips-opc.c | 212 #define WR_2 INSN_WRITE_2 macro 218 #define MOD_2 (WR_2|RD_2) 637 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 638 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 888 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 889 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 897 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, 898 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | mips16-opc.c | 166 #define WR_2 INSN_WRITE_2 macro 172 #define MOD_2 (WR_2|RD_2)
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H A D | mips-opc.c | 233 #define WR_2 INSN_WRITE_2 macro 240 #define MOD_2 (WR_2|RD_2) 522 {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, 1111 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1303 {"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, 1305 {"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, 1523 {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1524 {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1525 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, 1526 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, [all …]
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H A D | micromips-opc.c | 212 #define WR_2 INSN_WRITE_2 macro 218 #define MOD_2 (WR_2|RD_2) 637 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 638 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 888 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 889 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 897 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, 898 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | mips16-opc.c | 166 #define WR_2 INSN_WRITE_2 macro 172 #define MOD_2 (WR_2|RD_2)
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H A D | mips-opc.c | 233 #define WR_2 INSN_WRITE_2 macro 240 #define MOD_2 (WR_2|RD_2) 522 {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, 1111 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, 1303 {"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, 1305 {"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, 1523 {"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1524 {"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, 1525 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, 1526 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, [all …]
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H A D | micromips-opc.c | 212 #define WR_2 INSN_WRITE_2 macro 218 #define MOD_2 (WR_2|RD_2) 637 {"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 638 {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, 888 {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 889 {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, 897 {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, 898 {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
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H A D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): 348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): 358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
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