/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | micromips-opc.c | 62 #define WR_t INSN_WRITE_GPR_T macro 160 {"addi", "t,r,j", 0x10000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 167 {"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 385 {"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 }, 386 {"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 }, 412 {"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 }, 774 {"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, 0, WR_t, I1 }, 775 {"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_t, 0, I1 }, 1061 {"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t, 0, D32 }, 1062 {"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t, 0, D32 }, [all …]
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H A D | mips-opc.c | 46 #define WR_t INSN_WRITE_GPR_T macro 313 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 314 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 678 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 679 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 722 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 796 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 798 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 907 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, 1028 {"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR }, [all …]
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | mips-opc.c | 43 #define WR_t INSN_WRITE_GPR_T macro 203 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 204 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 223 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 526 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 527 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 566 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 632 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 633 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 712 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | mips-opc.c | 44 #define WR_t INSN_WRITE_GPR_T macro 288 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 289 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 312 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 687 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 761 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 765 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 768 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 849 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, 954 {"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR }, [all …]
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | mips-opc.c | 43 #define WR_t INSN_WRITE_GPR_T macro 147 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ 173 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, 174 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, 193 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, 497 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 }, 498 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 }, 602 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 }, 603 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 }, 677 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, [all …]
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | mips-opc.c | 43 #define WR_t INSN_WRITE_GPR_T macro 173 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 174 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 193 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 470 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 493 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 494 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 596 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 597 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 671 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | mips-opc.c | 43 #define WR_t INSN_WRITE_GPR_T macro 147 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ 173 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, 174 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, 193 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, 497 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 }, 498 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 }, 602 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 }, 603 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 }, 677 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, [all …]
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/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/mips/gnu/ |
H A D | mips-opc.c | 44 #define WR_t INSN_WRITE_GPR_T macro 222 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 223 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 246 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 570 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 571 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 610 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 682 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 683 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 763 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/ |
H A D | mips-opc.c | 42 #define WR_t INSN_WRITE_GPR_T macro 138 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ 161 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, 162 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, 177 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, 449 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, 450 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, 611 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, 764 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, 890 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, [all …]
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | mips-dis.c | 1071 #define WR_t INSN_WRITE_GPR_T macro 1562 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1563 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1602 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1666 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1667 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 1668 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 1670 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1673 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 1747 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2317 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2318 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2357 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2421 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2422 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2423 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2425 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2429 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2505 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2307 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2308 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2347 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2411 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2412 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2413 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2415 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2419 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2495 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2317 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2318 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2357 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2421 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2422 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2423 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2425 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2429 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2505 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2307 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2308 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2347 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2411 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2412 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2413 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2415 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2419 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2495 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2317 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2318 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2357 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2421 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2422 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2423 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2425 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2429 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2505 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2307 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2308 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2347 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2411 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2412 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2413 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2415 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2419 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2495 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T 2317 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2318 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2357 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2421 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2422 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2423 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2425 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2429 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2505 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | mips.c | 1119 #define WR_t INSN_WRITE_GPR_T macro 2317 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2318 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2357 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2421 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2422 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2423 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2425 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2429 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2505 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | mips.c | 1130 #define WR_t INSN_WRITE_GPR_T macro 2538 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2539 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2578 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2642 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2643 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2644 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2646 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2650 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2726 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, [all …]
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | ChangeLog-2013 | 344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | ChangeLog-2013 | 344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | ChangeLog-2013 | 344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | ChangeLog-2013 | 344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | ChangeLog-2013 | 344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | ChangeLog-2013 | 344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) 361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
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