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Searched refs:XVECLEN (Results 1 – 25 of 3756) sorted by relevance

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/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/
H A Dgenemit.c124 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
131 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
141 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
145 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
244 for (j = 0; j < XVECLEN (x, i); j++) in gen_exp()
287 if (i != XVECLEN (insn, 1) - 1) in gen_insn()
301 || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1)) in gen_insn()
320 if (j == XVECLEN (insn, 1)) in gen_insn()
369 if (XVECLEN (insn, 1) == 1) in gen_insn()
380 XVECLEN (insn, 1)); in gen_insn()
[all …]
H A Dgenconfig.c163 for (j = 0; j < XVECLEN (part, i); j++) in walk_insn_part()
178 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_insn()
199 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_expand()
222 for (i = 0; i < XVECLEN (split, 0); i++) in gen_split()
225 if (XVECLEN (split, 2) > max_insns_per_split) in gen_split()
226 max_insns_per_split = XVECLEN (split, 2); in gen_split()
236 for (i = 0; i < XVECLEN (peep, 0); i++) in gen_peephole()
247 for (i = XVECLEN (peep, 0) - 1; i >= 0; --i) in gen_peephole2()
251 for (i = XVECLEN (peep, 0) - 1, n = 0; i >= 0; --i) in gen_peephole2()
/dports/lang/gcc48/gcc-4.8.5/gcc/
H A Dgenemit.c124 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
131 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
141 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
145 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
244 for (j = 0; j < XVECLEN (x, i); j++) in gen_exp()
287 if (i != XVECLEN (insn, 1) - 1) in gen_insn()
301 || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1)) in gen_insn()
320 if (j == XVECLEN (insn, 1)) in gen_insn()
369 if (XVECLEN (insn, 1) == 1) in gen_insn()
380 XVECLEN (insn, 1)); in gen_insn()
[all …]
H A Dgenconfig.c163 for (j = 0; j < XVECLEN (part, i); j++) in walk_insn_part()
178 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_insn()
199 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_expand()
222 for (i = 0; i < XVECLEN (split, 0); i++) in gen_split()
225 if (XVECLEN (split, 2) > max_insns_per_split) in gen_split()
226 max_insns_per_split = XVECLEN (split, 2); in gen_split()
236 for (i = 0; i < XVECLEN (peep, 0); i++) in gen_peephole()
247 for (i = XVECLEN (peep, 0) - 1; i >= 0; --i) in gen_peephole2()
251 for (i = XVECLEN (peep, 0) - 1, n = 0; i >= 0; --i) in gen_peephole2()
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/
H A Dgenemit.c102 for (j = 0; j < XVECLEN (x, i); j++) in max_operand_1()
111 int len = XVECLEN (insn, arg); in max_operand_vec()
186 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
197 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
272 for (j = 0; j < XVECLEN (x, i); j++) in gen_exp()
312 if (i != XVECLEN (insn, 1) - 1) in gen_insn()
326 || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1)) in gen_insn()
345 if (j == XVECLEN (insn, 1)) in gen_insn()
394 if (XVECLEN (insn, 1) == 1) in gen_insn()
403 XVECLEN (insn, 1)); in gen_insn()
[all …]
H A Dgenconfig.c164 for (j = 0; j < XVECLEN (part, i); j++) in walk_insn_part()
179 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_insn()
200 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_expand()
223 for (i = 0; i < XVECLEN (split, 0); i++) in gen_split()
226 if (XVECLEN (split, 2) > max_insns_per_split) in gen_split()
227 max_insns_per_split = XVECLEN (split, 2); in gen_split()
237 for (i = 0; i < XVECLEN (peep, 0); i++) in gen_peephole()
248 for (i = XVECLEN (peep, 0) - 1; i >= 0; --i) in gen_peephole2()
252 for (i = XVECLEN (peep, 0) - 1, n = 0; i >= 0; --i) in gen_peephole2()
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/
H A Dgenemit.c102 for (j = 0; j < XVECLEN (x, i); j++) in max_operand_1()
111 int len = XVECLEN (insn, arg); in max_operand_vec()
186 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
197 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
272 for (j = 0; j < XVECLEN (x, i); j++) in gen_exp()
312 if (i != XVECLEN (insn, 1) - 1) in gen_insn()
326 || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1)) in gen_insn()
345 if (j == XVECLEN (insn, 1)) in gen_insn()
394 if (XVECLEN (insn, 1) == 1) in gen_insn()
403 XVECLEN (insn, 1)); in gen_insn()
[all …]
H A Dgenconfig.c164 for (j = 0; j < XVECLEN (part, i); j++) in walk_insn_part()
179 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_insn()
200 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_expand()
223 for (i = 0; i < XVECLEN (split, 0); i++) in gen_split()
226 if (XVECLEN (split, 2) > max_insns_per_split) in gen_split()
227 max_insns_per_split = XVECLEN (split, 2); in gen_split()
237 for (i = 0; i < XVECLEN (peep, 0); i++) in gen_peephole()
248 for (i = XVECLEN (peep, 0) - 1; i >= 0; --i) in gen_peephole2()
252 for (i = XVECLEN (peep, 0) - 1, n = 0; i >= 0; --i) in gen_peephole2()
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/
H A Dgenemit.c124 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
131 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
141 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
145 for (i = 0; i < XVECLEN (x, 2); i++) in gen_exp()
244 for (j = 0; j < XVECLEN (x, i); j++) in gen_exp()
287 if (i != XVECLEN (insn, 1) - 1) in gen_insn()
301 || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1)) in gen_insn()
320 if (j == XVECLEN (insn, 1)) in gen_insn()
369 if (XVECLEN (insn, 1) == 1) in gen_insn()
380 XVECLEN (insn, 1)); in gen_insn()
[all …]
H A Dgenconfig.c163 for (j = 0; j < XVECLEN (part, i); j++) in walk_insn_part()
178 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_insn()
199 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_expand()
222 for (i = 0; i < XVECLEN (split, 0); i++) in gen_split()
225 if (XVECLEN (split, 2) > max_insns_per_split) in gen_split()
226 max_insns_per_split = XVECLEN (split, 2); in gen_split()
236 for (i = 0; i < XVECLEN (peep, 0); i++) in gen_peephole()
247 for (i = XVECLEN (peep, 0) - 1; i >= 0; --i) in gen_peephole2()
251 for (i = XVECLEN (peep, 0) - 1, n = 0; i >= 0; --i) in gen_peephole2()
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/
H A Dgenemit.c102 for (j = 0; j < XVECLEN (x, i); j++) in max_operand_1()
111 int len = XVECLEN (insn, arg); in max_operand_vec()
182 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
189 for (i = 0; i < XVECLEN (x, 1); i++) in gen_exp()
298 for (j = 0; j < XVECLEN (x, i); j++) in gen_exp()
341 if (i != XVECLEN (insn, 1) - 1) in gen_insn()
355 || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1)) in gen_insn()
374 if (j == XVECLEN (insn, 1)) in gen_insn()
423 if (XVECLEN (insn, 1) == 1) in gen_insn()
432 XVECLEN (insn, 1)); in gen_insn()
[all …]
H A Dgenconfig.c165 for (j = 0; j < XVECLEN (part, i); j++) in walk_insn_part()
180 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_insn()
201 for (i = 0; i < XVECLEN (insn, 1); i++) in gen_expand()
224 for (i = 0; i < XVECLEN (split, 0); i++) in gen_split()
227 if (XVECLEN (split, 2) > max_insns_per_split) in gen_split()
228 max_insns_per_split = XVECLEN (split, 2); in gen_split()
238 for (i = 0; i < XVECLEN (peep, 0); i++) in gen_peephole()
249 for (i = XVECLEN (peep, 0) - 1; i >= 0; --i) in gen_peephole2()
253 for (i = XVECLEN (peep, 0) - 1, n = 0; i >= 0; --i) in gen_peephole2()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/lang/gcc9/gcc-9.4.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/lang/gcc10/gcc-10.3.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/config/arm/
H A Dldmstm.md37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
[all …]

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