| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 717 bits<5> Zm;
759 bits<5> Zm;
905 bits<5> Zm;
945 bits<5> Zm;
1093 bits<5> Zm;
1155 bits<5> Zm;
1182 bits<5> Zm;
1214 bits<5> Zm;
1243 bits<5> Zm;
1275 bits<5> Zm;
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
| H A D | aarch64-sve-asm.ll | 12 define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
13 …ale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
23 define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24 …ale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
34 define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
35 …x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
45 define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
46 … x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
56 … half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
57 ….h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 989 bits<5> Zm;
1075 bits<5> Zm;
1255 bits<5> Zm;
1302 bits<5> Zm;
1484 bits<5> Zm;
1558 bits<5> Zm;
1617 bits<5> Zm;
1656 bits<5> Zm;
1700 bits<5> Zm;
1736 bits<5> Zm;
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 989 bits<5> Zm;
1075 bits<5> Zm;
1255 bits<5> Zm;
1302 bits<5> Zm;
1484 bits<5> Zm;
1558 bits<5> Zm;
1617 bits<5> Zm;
1656 bits<5> Zm;
1700 bits<5> Zm;
1736 bits<5> Zm;
[all …]
|
| /dports/editors/libreoffice/libreoffice-7.2.6.2/writerperfect/qa/unit/data/draw/libmwaw/pass/ |
| H A D | SuperPaint_P_1.0.hqx | 16 `!!!5!!,[#!!-rJ$cH28!!!lmH!!!&3!#lKcq!!"Np53!+28!!$cp*!%J!"8!!Zm
18 mrJ!!6r82!!Mf!2X2!3J!&3!#lKcq!!"5p4)!'2B!!$,m%J%3!"F!!Zm)!!cq!!"
19 Kp5%!+2B!!1(m)3%J!"B!!Zm!!!6q!!"`pI!!q2F!!!2km!!!%J!#l`J!$2i!mhM
22 2!3J!&3!#lKcq!!"5p4)!'2J!!!Ek%J%3!"F!!Zm)!!cq!!"Kp5%!+2J!!!Rk)3%
23 J!"B!!Zm!!!6q!!"`pI!!q2J!!"$jm!!!%!!#l`J!$2i!mhMi!2Ki!!!9!!,Z(2i
27 -rJ!!BI8K!#Mj!!!4q5%")!!@!!,[!!!%rJ!!F2A`!2Mj!!!`q2!!!"!!!Zm)!!c
34 !!&,e%J!BqJ!!N[J5!4!!'!!#l`J!$2i!!'(e)3!Sq`!"!D(i)3%J!"B!!Zm!!!6
38 h%J%3!"F!!Zm)!!cq!!"Kp5%!+2X!!!Rh)3%J!"B!!Zm!!!6q!!"`pI!!q2X!!!M
41 !22i!!%re$`!)q`!!,rF2!3J!&3!#lKcq!!"5p4)!'2X!!$,h%J%3!"8!!Zm)!!c
42 q!!"Kp5%!+2X!pL%")!!@!!,[!!!%rJ!!F2A`!2Ml!!"`p[!!!"!!!Zm)!!cq!20
[all …]
|
| /dports/editors/libreoffice6/libreoffice-6.4.7.2/writerperfect/qa/unit/data/draw/libmwaw/pass/ |
| H A D | SuperPaint_P_1.0.hqx | 16 `!!!5!!,[#!!-rJ$cH28!!!lmH!!!&3!#lKcq!!"Np53!+28!!$cp*!%J!"8!!Zm
18 mrJ!!6r82!!Mf!2X2!3J!&3!#lKcq!!"5p4)!'2B!!$,m%J%3!"F!!Zm)!!cq!!"
19 Kp5%!+2B!!1(m)3%J!"B!!Zm!!!6q!!"`pI!!q2F!!!2km!!!%J!#l`J!$2i!mhM
22 2!3J!&3!#lKcq!!"5p4)!'2J!!!Ek%J%3!"F!!Zm)!!cq!!"Kp5%!+2J!!!Rk)3%
23 J!"B!!Zm!!!6q!!"`pI!!q2J!!"$jm!!!%!!#l`J!$2i!mhMi!2Ki!!!9!!,Z(2i
27 -rJ!!BI8K!#Mj!!!4q5%")!!@!!,[!!!%rJ!!F2A`!2Mj!!!`q2!!!"!!!Zm)!!c
34 !!&,e%J!BqJ!!N[J5!4!!'!!#l`J!$2i!!'(e)3!Sq`!"!D(i)3%J!"B!!Zm!!!6
38 h%J%3!"F!!Zm)!!cq!!"Kp5%!+2X!!!Rh)3%J!"B!!Zm!!!6q!!"`pI!!q2X!!!M
41 !22i!!%re$`!)q`!!,rF2!3J!&3!#lKcq!!"5p4)!'2X!!$,h%J%3!"8!!Zm)!!c
42 q!!"Kp5%!+2X!pL%")!!@!!,[!!!%rJ!!F2A`!2Ml!!"`p[!!!"!!!Zm)!!cq!20
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 906 bits<5> Zm;
957 bits<5> Zm;
1128 bits<5> Zm;
1175 bits<5> Zm;
1348 bits<5> Zm;
1415 bits<5> Zm;
1458 bits<5> Zm;
1497 bits<5> Zm;
1541 bits<5> Zm;
1577 bits<5> Zm;
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 906 bits<5> Zm;
957 bits<5> Zm;
1128 bits<5> Zm;
1175 bits<5> Zm;
1348 bits<5> Zm;
1415 bits<5> Zm;
1458 bits<5> Zm;
1497 bits<5> Zm;
1541 bits<5> Zm;
1577 bits<5> Zm;
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 906 bits<5> Zm;
957 bits<5> Zm;
1128 bits<5> Zm;
1175 bits<5> Zm;
1348 bits<5> Zm;
1415 bits<5> Zm;
1458 bits<5> Zm;
1497 bits<5> Zm;
1541 bits<5> Zm;
1577 bits<5> Zm;
[all …]
|
| /dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/AArch64/ |
| H A D | SVEInstrFormats.td | 711 bits<5> Zm;
864 bits<5> Zm;
889 bits<5> Zm;
1037 bits<5> Zm;
1099 bits<5> Zm;
1126 bits<5> Zm;
1158 bits<5> Zm;
1187 bits<5> Zm;
1219 bits<5> Zm;
1340 bits<5> Zm;
[all …]
|
| /dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/AArch64/ |
| H A D | SVEInstrFormats.td | 711 bits<5> Zm;
864 bits<5> Zm;
889 bits<5> Zm;
1037 bits<5> Zm;
1099 bits<5> Zm;
1126 bits<5> Zm;
1158 bits<5> Zm;
1187 bits<5> Zm;
1219 bits<5> Zm;
1340 bits<5> Zm;
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/AArch64/ |
| H A D | SVEInstrFormats.td | 711 bits<5> Zm;
864 bits<5> Zm;
889 bits<5> Zm;
1037 bits<5> Zm;
1099 bits<5> Zm;
1126 bits<5> Zm;
1158 bits<5> Zm;
1187 bits<5> Zm;
1219 bits<5> Zm;
1340 bits<5> Zm;
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 711 bits<5> Zm;
864 bits<5> Zm;
889 bits<5> Zm;
1037 bits<5> Zm;
1099 bits<5> Zm;
1126 bits<5> Zm;
1158 bits<5> Zm;
1187 bits<5> Zm;
1219 bits<5> Zm;
1340 bits<5> Zm;
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 711 bits<5> Zm;
864 bits<5> Zm;
889 bits<5> Zm;
1037 bits<5> Zm;
1099 bits<5> Zm;
1126 bits<5> Zm;
1158 bits<5> Zm;
1187 bits<5> Zm;
1219 bits<5> Zm;
1340 bits<5> Zm;
[all …]
|