1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Wei Lin<wei.w.lin@intel.com> 26 * Yuting Yang<yuting.yang@intel.com> 27 * Lina Sun<lina.sun@intel.com> 28 */ 29 30 #pragma once 31 32 #include "oscl_impl_linux.h" 33 #include "os_interface.h" 34 35 #ifdef __cplusplus 36 #define EXTERN_C extern "C" 37 #else 38 #define EXTERN_C 39 #endif 40 41 typedef void *DXVAUMD_RESOURCE; 42 43 typedef struct cm_tagLOOKUP_ENTRY { 44 void *pDirect3DSurface9; 45 DXVAUMD_RESOURCE SurfaceHandle; 46 UINT SurfaceAllocationIndex; 47 } CMLOOKUP_ENTRY, *PCMLOOKUP_ENTRY; 48 49 typedef struct cm_tagSURFACE_REG_TABLE { 50 UINT Count; 51 CMLOOKUP_ENTRY *pEntries; 52 } CMSURFACE_REG_TABLE, *PCMSURFACE_REG_TABLE; 53 54 typedef enum _CM_RETURN_CODE { 55 CM_SUCCESS = 0, 56 /* 57 * RANGE -1 ~ -9999 FOR EXTERNAL ERROR CODE 58 */ 59 CM_FAILURE = -1, 60 CM_NOT_IMPLEMENTED = -2, 61 CM_SURFACE_ALLOCATION_FAILURE = -3, 62 CM_OUT_OF_HOST_MEMORY = -4, 63 CM_SURFACE_FORMAT_NOT_SUPPORTED = -5, 64 CM_EXCEED_SURFACE_AMOUNT = -6, 65 CM_EXCEED_KERNEL_ARG_AMOUNT = -7, 66 CM_EXCEED_KERNEL_ARG_SIZE_IN_BYTE = -8, 67 CM_INVALID_ARG_INDEX = -9, 68 CM_INVALID_ARG_VALUE = -10, 69 CM_INVALID_ARG_SIZE = -11, 70 CM_INVALID_THREAD_INDEX = -12, 71 CM_INVALID_WIDTH = -13, 72 CM_INVALID_HEIGHT = -14, 73 CM_INVALID_DEPTH = -15, 74 CM_INVALID_COMMON_ISA = -16, 75 CM_EXCEED_MAX_KERNEL_PER_ENQUEUE = -21, 76 CM_EXCEED_MAX_KERNEL_SIZE_IN_BYTE = -22, 77 CM_EXCEED_MAX_THREAD_AMOUNT_PER_ENQUEUE = -23, 78 CM_INVALID_THREAD_SPACE = -25, 79 CM_EXCEED_MAX_TIMEOUT = -26, 80 CM_JITDLL_LOAD_FAILURE = -27, 81 CM_JIT_COMPILE_FAILURE = -28, 82 CM_JIT_COMPILESIM_FAILURE = -29, 83 CM_INVALID_THREAD_GROUP_SPACE = -30, 84 CM_THREAD_ARG_NOT_ALLOWED = -31, 85 CM_INVALID_GLOBAL_BUFFER_INDEX = -32, 86 CM_INVALID_BUFFER_HANDLER = -33, 87 CM_EXCEED_MAX_SLM_SIZE = -34, 88 CM_JITDLL_OLDER_THAN_ISA = -35, 89 CM_INVALID_HARDWARE_THREAD_NUMBER = -36, 90 CM_GTPIN_INVOKE_FAILURE = -37, 91 CM_INVALIDE_L3_CONFIGURATION = -38, 92 CM_INTEL_GFX_NOTFOUND = -40, 93 CM_GPUCOPY_INVALID_SYSMEM = -41, 94 CM_GPUCOPY_INVALID_WIDTH = -42, 95 CM_GPUCOPY_INVALID_STRIDE = -43, 96 CM_EVENT_DRIVEN_FAILURE = -44, 97 CM_LOCK_SURFACE_FAIL = -45, 98 CM_INVALID_GENX_BINARY = -46, 99 CM_FEATURE_NOT_SUPPORTED_IN_DRIVER = -47, 100 CM_QUERY_DLL_VERSION_FAILURE = -48, 101 CM_KERNELPAYLOAD_PERTHREADARG_MUTEX_FAIL = -49, 102 CM_KERNELPAYLOAD_PERKERNELARG_MUTEX_FAIL = -50, 103 CM_KERNELPAYLOAD_SETTING_FAILURE = -51, 104 CM_KERNELPAYLOAD_SURFACE_INVALID_BTINDEX = -52, 105 CM_NOT_SET_KERNEL_ARGUMENT = -53, 106 CM_GPUCOPY_INVALID_SURFACES = -54, 107 CM_GPUCOPY_INVALID_SIZE = -55, 108 CM_GPUCOPY_OUT_OF_RESOURCE = -56, 109 CM_SURFACE_DELAY_DESTROY = -58, 110 CM_FEATURE_NOT_SUPPORTED_BY_HARDWARE = -61, 111 CM_RESOURCE_USAGE_NOT_SUPPORT_READWRITE = -62, 112 CM_MULTIPLE_MIPLEVELS_NOT_SUPPORTED = -63, 113 CM_INVALID_UMD_CONTEXT = -64, 114 CM_INVALID_LIBVA_SURFACE = -65, 115 CM_INVALID_LIBVA_INITIALIZE = -66, 116 CM_KERNEL_THREADSPACE_NOT_SET = -67, 117 CM_INVALID_KERNEL_THREADSPACE = -68, 118 CM_KERNEL_THREADSPACE_THREADS_NOT_ASSOCIATED = -69, 119 CM_KERNEL_THREADSPACE_INTEGRITY_FAILED = -70, 120 CM_INVALID_USERPROVIDED_GENBINARY = -71, 121 CM_INVALID_PRIVATE_DATA = -72, 122 CM_INVALID_GENOS_RESOURCE_HANDLE = -73, 123 CM_SURFACE_CACHED = -74, 124 CM_SURFACE_IN_USE = -75, 125 CM_INVALID_GPUCOPY_KERNEL = -76, 126 CM_INVALID_DEPENDENCY_WITH_WALKING_PATTERN = -77, 127 CM_INVALID_MEDIA_WALKING_PATTERN = -78, 128 CM_EXCEED_MAX_POWER_OPTION_FOR_PLATFORM = -80, 129 CM_INVALID_KERNEL_THREADGROUPSPACE = -81, 130 CM_INVALID_KERNEL_SPILL_CODE = -82, 131 CM_UMD_DRIVER_NOT_SUPPORTED = -83, 132 CM_INVALID_GPU_FREQUENCY_VALUE = -84, 133 CM_SYSTEM_MEMORY_NOT_4KPAGE_ALIGNED = -85, 134 CM_KERNEL_ARG_SETTING_FAILED = -86, 135 CM_NO_AVAILABLE_SURFACE = -87, 136 CM_VA_SURFACE_NOT_SUPPORTED = -88, 137 CM_TOO_MUCH_THREADS = -89, 138 CM_NULL_POINTER = -90, 139 140 /* 141 * RANGE -10000 ~ -19999 FOR INTERNAL ERROR CODE 142 */ 143 CM_INTERNAL_ERROR_CODE_OFFSET = -10000, 144 145 /* 146 * RANGE <=-20000 AREAD FOR MOST STATUS CONVERSION 147 */ 148 CM_GENOS_STATUS_CONVERTED_CODE_OFFSET = -20000 149 } CM_RETURN_CODE; 150 151 #define GENHW_CM_MAX_THREADS "CmMaxThreads" 152 153 #define CM_HAL_LOCKFLAG_READONLY 0x00000001 154 #define CM_HAL_LOCKFLAG_WRITEONLY 0x00000002 155 156 #define CM_BATCH_BUFFER_REUSE_ENABLE 1 157 #define CM_MAX_TASKS_DEFAULT 4 158 #define CM_MAXIMUM_TASKS 64 159 #define CM_MAX_TASKS_EU_SATURATION 4 160 161 #define CM_KERNEL_BINARY_BLOCK_SIZE 65536 162 #define CM_MAX_KERNELS_PER_TASK 16 163 #define CM_MAX_SPILL_SIZE_PER_THREAD_IVB 11264 164 #define CM_MAX_SPILL_SIZE_PER_THREAD_HSW_BDW 131072 165 #define CM_MAX_SPILL_SIZE_PER_THREAD_DEFAULT CM_MAX_SPILL_SIZE_PER_THREAD 166 167 #define CM_MAX_BUFFER_SURFACE_TABLE_SIZE 256 168 #define CM_MAX_2D_SURFACE_UP_TABLE_SIZE 512 169 #define CM_MAX_2D_SURFACE_TABLE_SIZE 256 170 #define CM_MAX_3D_SURFACE_TABLE_SIZE 64 171 #define CM_MAX_USER_THREADS 261121 172 #define CM_MAX_USER_THREADS_NO_THREADARG 261121 173 #define CM_MAX_USER_THREADS_PER_MEDIA_WALKER (CM_MAX_THREADSPACE_WIDTH * CM_MAX_THREADSPACE_HEIGHT * CM_THREADSPACE_MAX_COLOR_COUNT) 174 #define CM_MAX_USER_THREADS_PER_MEDIA_WALKER_SKL_PLUS (CM_MAX_THREADSPACE_WIDTH_SKLUP * CM_MAX_THREADSPACE_HEIGHT_SKLUP * CM_THREADSPACE_MAX_COLOR_COUNT) 175 176 #define MAX_THREAD_SPACE_WIDTH_PERGROUP 64 177 #define MAX_THREAD_SPACE_HEIGHT_PERGROUP 64 178 #define CM_MAX_BB_SIZE 16777216 179 #define CM_MAX_ARGS_PER_KERNEL 255 180 #define CM_MAX_THREAD_PAYLOAD_SIZE 2016 181 #define CM_MAX_ARG_BYTE_PER_KERNEL CM_MAX_THREAD_PAYLOAD_SIZE 182 #define CM_EXTRA_BB_SPACE 256 183 #define CM_MAX_STATIC_SURFACE_STATES_PER_BT 256 184 #define CM_MAX_SURFACE_STATES_PER_BT 64 185 #define CM_MAX_SURFACE_STATES 256 186 #define CM_PAYLOAD_OFFSET 32 187 #define CM_PER_KERNEL_ARG_VAL 1 188 #define CM_MAX_CURBE_SIZE_PER_TASK 8192 189 #define CM_MAX_CURBE_SIZE_PER_KERNEL CM_MAX_THREAD_PAYLOAD_SIZE 190 #define CM_MAX_THREAD_WIDTH 511 191 #define CM_MAX_INDIRECT_DATA_SIZE_PER_KERNEL 1984 192 #define CM_HAL_MAX_DEPENDENCY_COUNT 8 193 194 #define CM_MAX_SIP_SIZE 0x1800 195 #define CM_DEBUG_SURFACE_INDEX 252 196 #define CM_DEBUG_SURFACE_SIZE 0x300000 197 #define CM_SYNC_QWORD_PER_TASK 2 198 199 #define CM_NULL_SURFACE 0xFFFF 200 #define CM_SURFACE_MASK 0xFFFF 201 #define CM_MEMORY_OBJECT_CONTROL_MASK 0xFFFF0000 202 #define CM_DEFAULT_CACHE_TYPE 0xFF00 203 204 #define CM_NULL_SURFACE_BINDING_INDEX 0 205 #define CM_MAX_GLOBAL_SURFACE_NUMBER 4 206 207 #define CM_BINDING_START_INDEX_OF_GLOBAL_SURFACE(pState) (pState->Platform.eRenderCoreFamily >= IGFX_GEN9_CORE ? 1 : 243) 208 #define CM_BINDING_START_INDEX_OF_GENERAL_SURFACE(pState) (pState->Platform.eRenderCoreFamily >= IGFX_GEN9_CORE ? 8 : 1) 209 #define CM_RESERVED_SURFACE_NUMBER_FROM_0(pState) (pState->Platform.eRenderCoreFamily >= IGFX_GEN9_CORE ? 8 : 1) 210 211 #define CM_RESERVED_SURFACE_NUMBER_FOR_KERNEL_DEBUG 1 212 #define CM_GPUWALKER_IMPLICIT_ARG_NUM 6 213 214 #define CM_KNL_SZ_BINARY_SIZE 4 215 #define CM_KNL_SZ_BINARY_OFFSET 4 216 #define CM_KNL_SZ_THREAD_COUNT 4 217 #define CM_KNL_SZ_ARG_COUNT 4 218 219 #define CM_KNL_POS_BINARY_SIZE 0 220 #define CM_KNL_POS_BINARY_OFFSET (CM_KNL_POS_BINARY_SIZE +\ 221 CM_KNL_SZ_BINARY_SIZE) 222 #define CM_KNL_POS_THREAD_COUNT (CM_KNL_POS_BINARY_OFFSET +\ 223 CM_KNL_SZ_BINARY_OFFSET) 224 #define CM_KNL_POS_ARG_COUNT (CM_KNL_POS_THREAD_COUNT +\ 225 CM_KNL_SZ_THREAD_COUNT) 226 #define CM_KNL_POS_ARG_BLOCK_BASE (CM_KNL_POS_ARG_COUNT +\ 227 CM_KNL_SZ_ARG_COUNT) 228 229 #define CM_KNL_SZ_ARG_KIND 2 230 #define CM_KNL_SZ_ARG_UNIT_COUNT 2 231 #define CM_KNL_SZ_ARG_UNIT_SIZE 2 232 #define CM_KNL_SZ_ARG_PAYLOAD_OFFSET 2 233 #define CM_KNL_SZ_ARG_VALUE_OFFSET 4 234 #define CM_KNL_SZ_ARG_BLOCK (CM_KNL_SZ_ARG_KIND +\ 235 CM_KNL_SZ_ARG_UNIT_COUNT +\ 236 CM_KNL_SZ_ARG_UNIT_SIZE +\ 237 CM_KNL_SZ_ARG_PAYLOAD_OFFSET +\ 238 CM_KNL_SZ_ARG_VALUE_OFFSET) 239 240 #define CM_KNL_RPOS_ARG_KIND 0 241 #define CM_KNL_RPOS_ARG_UNIT_COUNT (CM_KNL_RPOS_ARG_KIND +\ 242 CM_KNL_SZ_ARG_KIND) 243 #define CM_KNL_RPOS_ARG_UNIT_SIZE (CM_KNL_RPOS_ARG_UNIT_COUNT +\ 244 CM_KNL_SZ_ARG_UNIT_COUNT) 245 #define CM_KNL_RPOS_ARG_PAYLOAD_OFFSET (CM_KNL_RPOS_ARG_UNIT_SIZE +\ 246 CM_KNL_SZ_ARG_UNIT_SIZE) 247 #define CM_KNL_RPOS_ARG_VAL_OFFSET (CM_KNL_RPOS_ARG_PAYLOAD_OFFSET +\ 248 CM_KNL_SZ_ARG_PAYLOAD_OFFSET) 249 250 #define CM_INVALID_INDEX -1 251 252 #define CM_KERNEL_FLAGS_CURBE 0x00000001 253 #define CM_KERNEL_FLAGS_NONSTALLING_SCOREBOARD 0x00000002 254 255 #define ADDRESS_PAGE_ALIGNMENT_MASK_X64 0xFFFFFFFFFFFFF000ULL 256 #define ADDRESS_PAGE_ALIGNMENT_MASK_X86 0xFFFFF000 257 258 #define CM_INVALID_MEMOBJCTL 0xFF 259 #define CM_MEMOBJCTL_CACHE_MASK 0xFF00 260 261 #define CM_NO_KERNEL_SYNC 0 262 263 #define CM_HINTS_MASK_MEDIAOBJECT 0x1 264 #define CM_HINTS_MASK_KERNEL_GROUPS 0xE 265 #define CM_HINTS_NUM_BITS_WALK_OBJ 0x1 266 #define CM_HINTS_LEASTBIT_MASK 1 267 #define CM_HINTS_DEFAULT_NUM_KERNEL_GRP 1 268 #define CM_DEFAULT_THREAD_DEPENDENCY_MASK 0xFF 269 #define CM_REUSE_DEPENDENCY_MASK 0x1 270 #define CM_RESET_DEPENDENCY_MASK 0x2 271 #define CM_NO_BATCH_BUFFER_REUSE 0x4 272 #define CM_NO_BATCH_BUFFER_REUSE_BIT_POS 0x2 273 #define CM_SCOREBOARD_MASK_POS_IN_MEDIA_OBJECT_CMD 0x5 274 #define CM_HINTS_MASK_NUM_TASKS 0x70 275 #define CM_HINTS_NUM_BITS_TASK_POS 0x4 276 277 #define CM_GEN7_5_HW_THREADS_PER_EU 7 278 #define CM_GEN7_5_GT1_EUS_PER_SUBSLICE 10 279 #define CM_GEN7_5_GT2_EUS_PER_SUBSLICE 10 280 #define CM_GEN7_5_GT3_EUS_PER_SUBSLICE 10 281 #define CM_GEN7_5_GT1_SLICE_NUM 1 282 #define CM_GEN7_5_GT2_SLICE_NUM 1 283 #define CM_GEN7_5_GT3_SLICE_NUM 2 284 #define CM_GEN7_5_GT1_SUBSLICE_NUM 1 285 #define CM_GEN7_5_GT2_SUBSLICE_NUM 2 286 #define CM_GEN7_5_GT3_SUBSLICE_NUM 4 287 288 #define CM_GEN8_HW_THREADS_PER_EU 7 289 #define CM_GEN8_GT1_EUS_PER_SUBSLICE 6 290 #define CM_GEN8_GT2_EUS_PER_SUBSLICE 8 291 #define CM_GEN8_GT3_EUS_PER_SUBSLICE 8 292 #define CM_GEN8_GT1_SLICE_NUM 1 293 #define CM_GEN8_GT2_SLICE_NUM 1 294 #define CM_GEN8_GT3_SLICE_NUM 2 295 #define CM_GEN8_GT1_SUBSLICE_NUM 2 296 #define CM_GEN8_GT2_SUBSLICE_NUM 3 297 #define CM_GEN8_GT3_SUBSLICE_NUM 6 298 299 #define CM_GEN8LP_HW_THREADS_PER_EU 7 300 #define CM_GEN8LP_EUS_PER_SUBSLICE 8 301 #define CM_GEN8LP_SLICE_NUM 1 302 #define CM_GEN8LP_SUBSLICE_NUM 2 303 304 #define CM_GEN9_SKL_HW_THREADS_PER_EU 7 305 #define CM_GEN9_SKL_EUS_PER_SUBSLICE 8 306 307 #define CM_GEN9_GT1_EUS_PER_SUBSLICE 6 308 #define CM_GEN9_GT1_SUBSLICE_NUM 2 309 #define CM_GEN9_GT1_SLICE_NUM 1 310 311 #define CM_GEN9_GT1_5_EUS_PER_SUBSLICE 6 312 #define CM_GEN9_GT1_5_SUBSLICE_NUM 3 313 #define CM_GEN9_GT1_5_SLICE_NUM 1 314 315 #define CM_GEN9_GT2_EUS_PER_SUBSLICE 8 316 #define CM_GEN9_GT2_SUBSLICE_NUM 3 317 #define CM_GEN9_GT2_SLICE_NUM 1 318 319 #define CM_GEN9_GT3_EUS_PER_SUBSLICE 8 320 #define CM_GEN9_GT3_SUBSLICE_NUM 6 321 #define CM_GEN9_GT3_SLICE_NUM 2 322 323 #define CM_GEN9_GT4_EUS_PER_SUBSLICE 8 324 #define CM_GEN9_GT4_SUBSLICE_NUM 9 325 #define CM_GEN9_GT4_SLICE_NUM 3 326 327 // BXT 328 #define CM_GEN9_BXT_HW_THREADS_PER_EU 6 329 #define CM_GEN9_BXT_C_EUS_PER_SUBSLICE 6 330 #define CM_GEN9_BXT_A_EUS_PER_SUBSLICE 6 331 #define CM_GEN9_BXT_X_EUS_PER_SUBSLICE 8 332 #define CM_GEN9_BXT_SLICE_NUM 1 333 334 #define CM_GEN9_BXT_A_SUBSLICE_NUM 3 335 #define CM_GEN9_BXT_C_SUBSLICE_NUM 2 336 #define CM_GEN9_BXT_A_MAX_EUS_PER_POOL 9 337 #define CM_GEN9_BXT_C_MAX_EUS_PER_POOL 12 338 339 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE 0 340 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_DISABLE 1 341 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_MASK 1 342 343 #define CM_DEVICE_CREATE_OPTION_TDR_DISABLE 64 344 345 #define CM_DEVICE_CREATE_OPTION_SURFACE_REUSE_ENABLE 1024 346 347 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_OFFSET 1 348 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_MASK (7 << CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_OFFSET) 349 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_16K_STEP 16384 350 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_16K 1 351 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_32K 2 352 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_48K 3 353 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_64K 4 354 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_80K 5 355 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_96K 6 356 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_112K 7 357 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_128K 0 358 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_DEFAULT CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_128K 359 360 #define CM_DEVICE_CONFIG_TASK_NUM_OFFSET 4 361 #define CM_DEVICE_CONFIG_TASK_NUM_MASK (3 << CM_DEVICE_CONFIG_TASK_NUM_OFFSET) 362 #define CM_DEVICE_CONFIG_TASK_NUM_DEFAULT 0 363 #define CM_DEVICE_CONFIG_TASK_NUM_8 1 364 #define CM_DEVICE_CONFIG_TASK_NUM_12 2 365 #define CM_DEVICE_CONFIG_TASK_NUM_16 3 366 #define CM_DEVICE_CONFIG_TASK_NUM_STEP 4 367 368 #define CM_DEVICE_CONFIG_MEDIA_RESET_OFFSET 7 369 #define CM_DEVICE_CONFIG_MEDIA_RESET_ENABLE (1 << CM_DEVICE_CONFIG_MEDIA_RESET_OFFSET) 370 371 #define CM_DEVICE_CONFIG_EXTRA_TASK_NUM_OFFSET 8 372 #define CM_DEVICE_CONFIG_EXTRA_TASK_NUM_MASK (3 << CM_DEVICE_CONFIG_EXTRA_TASK_NUM_OFFSET) 373 #define CM_DEVICE_CONFIG_EXTRA_TASK_NUM_4 3 374 375 #define CM_DEVICE_CONFIG_SLICESHUTDOWN_OFFSET 10 376 #define CM_DEVICE_CONFIG_SLICESHUTDOWN_ENABLE (1 << CM_DEVICE_CONFIG_SLICESHUTDOWN_OFFSET) 377 378 #define CM_DEVICE_CONFIG_SURFACE_REUSE_ENABLE 11 379 380 #define CM_DEVICE_CONFIG_GPUCONTEXT_OFFSET 12 381 #define CM_DEVICE_CONFIG_GPUCONTEXT_ENABLE (1 << CM_DEVICE_CONFIG_GPUCONTEXT_OFFSET) 382 383 #define CM_DEVICE_CONFIG_SLM_MODE_OFFSET 13 384 #define CM_DEVICE_CONFIG_SLM_MODE_ENABLE (1 << CM_DEVICE_CONFIG_SLM_MODE_OFFSET) 385 386 #define CM_DEVICE_CREATE_OPTION_DEFAULT ((CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE) \ 387 | (CM_DEVICE_CONFIG_SLM_MODE_ENABLE)) 388 // VP9 config : 389 // Scratch space size :16k 390 // Number of task: 16 391 // Media Reset Option : TRUE 392 // Extra task num: 4 393 #define CM_DEVICE_CREATE_OPTION_FOR_VP9 ((CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE) \ 394 | (CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_16K << CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_OFFSET) \ 395 | (CM_DEVICE_CONFIG_TASK_NUM_16 << CM_DEVICE_CONFIG_TASK_NUM_OFFSET) \ 396 | (CM_DEVICE_CONFIG_MEDIA_RESET_ENABLE) \ 397 | (CM_DEVICE_CONFIG_EXTRA_TASK_NUM_4 << CM_DEVICE_CONFIG_EXTRA_TASK_NUM_OFFSET)\ 398 | (CM_DEVICE_CONFIG_GPUCONTEXT_ENABLE)) 399 400 #define CM_ARGUMENT_SURFACE_SIZE 4 401 402 #define SIWA_ONLY_HSW_A0 SIWA_ONLY_A0 403 #define SIWA_ONLY_HSW_A1 SIWA_ONLY_A1 404 #define SIWA_ONLY_HSW_B0 SIWA_ONLY_A2 405 #define SIWA_ONLY_HSW_C0 SIWA_ONLY_A3 406 #define SIWA_ONLY_HSW_D0 SIWA_ONLY_A4 407 408 #define SIWA_ONLY_BDW_A0 SIWA_ONLY_A0 409 #define SIWA_ONLY_BDW_E0 SIWA_ONLY_A5 410 #define SIWA_ONLY_BDW_F0 SIWA_ONLY_A6 411 #define SIWA_UNTIL_BDW_F0 SIWA_UNTIL_A6 412 #define SIWA_UNTIL_BDW_G0 SIWA_UNTIL_A7 413 414 #define MAX_STEPPING_NUM 10 415 416 #define CM_26ZI_BLOCK_WIDTH 16 417 #define CM_26ZI_BLOCK_HEIGHT 8 418 419 #define CM_NUM_DWORD_FOR_MW_PARAM 16 420 421 #define CM_DDI_1_0 100 422 #define CM_DDI_1_1 101 423 #define CM_DDI_1_2 102 424 #define CM_DDI_1_3 103 425 #define CM_DDI_1_4 104 426 #define CM_DDI_2_0 200 427 #define CM_DDI_2_1 201 428 #define CM_DDI_2_2 202 429 #define CM_DDI_2_3 203 430 #define CM_DDI_2_4 204 431 #define CM_DDI_3_0 300 432 #define CM_DDI_4_0 400 433 #define CM_DDI_5_0 500 434 435 #define DXVA_CM_VERSION CM_DDI_5_0 436 #define VA_CM_VERSION DXVA_CM_VERSION 437 438 typedef struct _CM_HAL_STATE *PCM_HAL_STATE; 439 typedef struct _CM_HAL_TASK_PARAM *PCM_HAL_TASK_PARAM; 440 typedef struct _CM_HAL_TASK_TIMESTAMP *PCM_HAL_TASK_TIMESTAMP; 441 typedef struct _CM_HAL_KERNEL_PARAM *PCM_HAL_KERNEL_PARAM; 442 443 typedef enum _CM_HAL_TASK_STATUS { 444 CM_TASK_QUEUED, 445 CM_TASK_IN_PROGRESS, 446 CM_TASK_FINISHED 447 } CM_HAL_TASK_STATUS; 448 449 typedef enum { 450 GENX_NONE = -1, 451 GENX_HSW = 2, 452 GENX_BDW = 3, 453 GENX_CHV = 4, 454 GENX_SKL = 5, 455 GENX_BXT = 6, 456 ALL = 8 457 } CISA_GEN_ID; 458 459 typedef enum _CM_BUFFER_TYPE { 460 CM_BUFFER_N = 0, 461 CM_BUFFER_UP = 1, 462 CM_BUFFER_GLOBAL = 3 463 } CM_BUFFER_TYPE; 464 465 typedef struct _CM_HAL_MAX_VALUES { 466 UINT iMaxTasks; 467 UINT iMaxKernelsPerTask; 468 UINT iMaxKernelBinarySize; 469 UINT iMaxSpillSizePerHwThread; 470 UINT iMaxBufferTableSize; 471 UINT iMax2DSurfaceTableSize; 472 UINT iMax3DSurfaceTableSize; 473 UINT iMaxArgsPerKernel; 474 UINT iMaxArgByteSizePerKernel; 475 UINT iMaxSurfacesPerKernel; 476 UINT iMaxHwThreads; 477 UINT iMaxUserThreadsPerTask; 478 UINT iMaxUserThreadsPerTaskNoThreadArg; 479 } CM_HAL_MAX_VALUES, *PCM_HAL_MAX_VALUES; 480 481 typedef struct _CM_HAL_MAX_VALUES_EX { 482 UINT iMax2DUPSurfaceTableSize; 483 UINT iMaxCURBESizePerKernel; 484 UINT iMaxCURBESizePerTask; 485 UINT iMaxIndirectDataSizePerKernel; 486 UINT iMaxUserThreadsPerMediaWalker; 487 UINT iMaxUserThreadsPerThreadGroup; 488 } CM_HAL_MAX_VALUES_EX, *PCM_HAL_MAX_VALUES_EX; 489 490 typedef struct _CM_INDIRECT_SURFACE_INFO { 491 WORD iKind; 492 WORD iSurfaceIndex; 493 WORD iBindingTableIndex; 494 } CM_INDIRECT_SURFACE_INFO, *PCM_INDIRECT_SURFACE_INFO; 495 496 typedef struct _CM_HAL_CREATE_PARAM { 497 BOOL DisableScratchSpace; 498 UINT ScratchSpaceSize; 499 UINT MaxTaskNumber; 500 BOOL bMediaReset; 501 BOOL bRequestSliceShutdown; 502 BOOL EnableSurfaceReuse; 503 BOOL bRequestCustomGpuContext; 504 BOOL bSLMMode; 505 } CM_HAL_CREATE_PARAM, *PCM_HAL_CREATE_PARAM; 506 507 typedef struct _CM_HAL_DEVICE_PARAM { 508 UINT iMaxTasks; 509 UINT iMaxKernelsPerTask; 510 UINT iMaxKernelBinarySize; 511 UINT iMaxBufferTableSize; 512 UINT iMax2DSurfaceUPTableSize; 513 UINT iMax2DSurfaceTableSize; 514 UINT iMax3DSurfaceTableSize; 515 UINT iMaxPerThreadScratchSpaceSize; 516 } CM_HAL_DEVICE_PARAM, *PCM_HAL_DEVICE_PARAM; 517 518 typedef struct _CM_HAL_SURFACE_ENTRY_INFO { 519 UINT dwWidth; 520 UINT dwHeight; 521 UINT dwDepth; 522 523 GFX_DDIFORMAT dwFormat; 524 UINT dwPlaneIndex; 525 526 UINT dwPitch; 527 UINT dwSurfaceBaseAddress; 528 UINT8 u8TiledSurface; 529 UINT8 u8TileWalk; 530 UINT dwXOffset; 531 UINT dwYOffset; 532 } CM_HAL_SURFACE_ENTRY_INFO, CM_SURFACE_DETAILS, *PCM_HAL_SURFACE_ENTRY_INFO; 533 534 typedef struct _CM_HAL_SURFACE_ENTRY_INFO_ARRAY { 535 UINT dwMaxEntryNum; 536 UINT dwUsedIndex; 537 PCM_HAL_SURFACE_ENTRY_INFO pSurfEntryInfos; 538 UINT dwGlobalSurfNum; 539 PCM_HAL_SURFACE_ENTRY_INFO pGlobalSurfInfos; 540 } CM_HAL_SURFACE_ENTRY_INFO_ARRAY; 541 542 typedef struct _CM_HAL_SURFACE_ENTRY_INFO_ARRAYS { 543 UINT dwKrnNum; 544 CM_HAL_SURFACE_ENTRY_INFO_ARRAY *pSurfEntryInfosArray; 545 } CM_HAL_SURFACE_ENTRY_INFO_ARRAYS; 546 547 typedef struct _CM_HAL_SCOREBOARD_XY { 548 INT x; 549 INT y; 550 } CM_HAL_SCOREBOARD_XY, *PCM_HAL_SCOREBOARD_XY; 551 552 typedef struct _CM_HAL_SCOREBOARD_XY_MASK { 553 INT x; 554 INT y; 555 BYTE mask; 556 BYTE resetMask; 557 } CM_HAL_SCOREBOARD_XY_MASK, *PCM_HAL_SCOREBOARD_XY_MASK; 558 559 typedef struct _CM_HAL_MASK_AND_RESET { 560 BYTE mask; 561 BYTE resetMask; 562 } CM_HAL_MASK_AND_RESET, *PCM_HAL_MASK_AND_RESET; 563 564 typedef enum _CM_DEPENDENCY_PATTERN { 565 CM_DEPENDENCY_NONE = 0, 566 CM_DEPENDENCY_WAVEFRONT = 1, 567 CM_DEPENDENCY_WAVEFRONT26 = 2, 568 CM_DEPENDENCY_VERTICAL = 3, 569 CM_DEPENDENCY_HORIZONTAL = 4, 570 CM_DEPENDENCY_WAVEFRONT26Z = 5, 571 CM_DEPENDENCY_WAVEFRONT26ZI = 8 572 } CM_DEPENDENCY_PATTERN; 573 574 #define CM_HAL_DEPENDENCY_PATTERN CM_DEPENDENCY_PATTERN 575 #define _CM_HAL_DEPENDENCY_PATTERN _CM_DEPENDENCY_PATTERN 576 577 typedef enum _CM_26ZI_DISPATCH_PATTERN { 578 VVERTICAL_HVERTICAL_26 = 0, 579 VVERTICAL_HHORIZONTAL_26 = 1, 580 VVERTICAL26_HHORIZONTAL26 = 2, 581 VVERTICAL1X26_HHORIZONTAL1X26 = 3 582 } CM_26ZI_DISPATCH_PATTERN; 583 #define _CM_HAL_26ZI_DISPATCH_PATTERN _CM_26ZI_DISPATCH_PATTERN 584 #define CM_HAL_26ZI_DISPATCH_PATTERN CM_26ZI_DISPATCH_PATTERN 585 typedef enum _CM_HAL_WALKING_PATTERN { 586 CM_WALK_DEFAULT = 0, 587 CM_WALK_WAVEFRONT = 1, 588 CM_WALK_WAVEFRONT26 = 2, 589 CM_WALK_VERTICAL = 3, 590 CM_WALK_HORIZONTAL = 4 591 } CM_HAL_WALKING_PATTERN; 592 593 typedef struct _CM_HAL_WALKING_PARAMETERS { 594 DWORD Value[CM_NUM_DWORD_FOR_MW_PARAM]; 595 } CM_HAL_WALKING_PARAMETERS, *PCM_HAL_WALKING_PARAMETERS; 596 597 typedef struct _CM_HAL_DEPENDENCY { 598 UINT count; 599 INT deltaX[CM_HAL_MAX_DEPENDENCY_COUNT]; 600 INT deltaY[CM_HAL_MAX_DEPENDENCY_COUNT]; 601 } CM_HAL_DEPENDENCY; 602 603 typedef enum _CM_HAL_BB_DIRTY_STATUS { 604 CM_HAL_BB_CLEAN = 0, 605 CM_HAL_BB_DIRTY = 1 606 } CM_HAL_BB_DIRTY_STATUS, *PCM_HAL_BB_DIRTY_STATUS; 607 608 typedef struct _CM_HAL_WAVEFRONT26Z_DISPATCH_INFO { 609 UINT numWaves; 610 PUINT pNumThreadsInWave; 611 } CM_HAL_WAVEFRONT26Z_DISPATCH_INFO; 612 613 typedef struct _CM_HAL_KERNEL_SLICE_SUBSLICE { 614 UINT slice; 615 UINT subSlice; 616 } CM_HAL_KERNEL_SLICE_SUBSLICE, *PCM_HAL_KERNEL_SLICE_SUBSLICE; 617 618 typedef struct _CM_HAL_KERNEL_SUBLICE_INFO { 619 UINT numSubSlices; 620 UINT counter; 621 PCM_HAL_KERNEL_SLICE_SUBSLICE pDestination; 622 } CM_HAL_KERNEL_SUBSLICE_INFO, *PCM_HAL_KERNEL_SUBSLICE_INFO; 623 624 typedef struct _CM_HAL_PLATFORM_SUBSLICE_INFO { 625 UINT numSlices; 626 UINT numSubSlices; 627 UINT numEUsPerSubSlice; 628 UINT numHWThreadsPerEU; 629 } CM_HAL_PLATFORM_SUBSLICE_INFO, *PCM_HAL_PLATFORM_SUBSLICE_INFO; 630 631 typedef struct _CM_HAL_PARALLELISM_GRAPH_INFO { 632 UINT maxParallelism; 633 UINT numMaxRepeat; 634 UINT numSteps; 635 } CM_HAL_PARALLELISM_GRAPH_INFO, *PCM_HAL_PARALLELISM_GRAPH_INFO; 636 637 typedef struct _CM_HAL_KERNEL_GROUP_INFO { 638 UINT numKernelsFinished; 639 UINT numKernelsInGroup; 640 UINT groupFinished; 641 UINT numStepsInGrp; 642 UINT freqDispatch; 643 } CM_HAL_KERNEL_GROUP_INFO, *PCM_HAL_KERNEL_GROUP_INFO; 644 645 typedef struct _CM_HAL_MAX_HW_THREAD_VALUES { 646 UINT registryValue; 647 UINT APIValue; 648 } CM_HAL_MAX_HW_THREAD_VALUES; 649 650 typedef enum _DXVA_CM_SET_TYPE { 651 DXVA_CM_MAX_HW_THREADS, 652 DXVA_CM_MAX_HW_L3_CONFIG 653 } DXVA_CM_SET_TYPE; 654 655 typedef struct _CM_HAL_MAX_SET_CAPS_PARAM { 656 DXVA_CM_SET_TYPE Type; 657 union { 658 UINT MaxValue; 659 struct { 660 UINT L3_SQCREG1; 661 UINT L3_CNTLREG2; 662 UINT L3_CNTLREG3; 663 UINT L3_CNTLREG; 664 }; 665 }; 666 667 } CM_HAL_MAX_SET_CAPS_PARAM, *PCM_HAL_MAX_SET_CAPS_PARAM; 668 669 typedef struct _CM_HAL_EXEC_GROUP_TASK_PARAM { 670 PCM_HAL_KERNEL_PARAM *pKernels; 671 PUINT piKernelSizes; 672 UINT iNumKernels; 673 INT iTaskIdOut; 674 UINT threadSpaceWidth; 675 UINT threadSpaceHeight; 676 UINT groupSpaceWidth; 677 UINT groupSpaceHeight; 678 UINT iSLMSize; 679 CM_HAL_SURFACE_ENTRY_INFO_ARRAYS SurEntryInfoArrays; 680 PVOID OsData; 681 UINT64 uiSyncBitmap; 682 BOOL bGlobalSurfaceUsed; 683 PUINT piKernelCurbeOffset; 684 UINT iPreemptionMode; 685 BOOL bKernelDebugEnabled; 686 } CM_HAL_EXEC_TASK_GROUP_PARAM, *PCM_HAL_EXEC_GROUP_TASK_PARAM; 687 688 typedef struct _CM_HAL_EXEC_HINTS_TASK_PARAM { 689 PCM_HAL_KERNEL_PARAM *pKernels; 690 PUINT piKernelSizes; 691 UINT iNumKernels; 692 INT iTaskIdOut; 693 UINT iHints; 694 UINT iNumTasksGenerated; 695 BOOLEAN isLastTask; 696 PVOID OsData; 697 PUINT piKernelCurbeOffset; 698 } CM_HAL_EXEC_HINTS_TASK_PARAM, *PCM_HAL_EXEC_HINTS_TASK_PARAM; 699 700 typedef struct _CM_HAL_QUERY_TASK_PARAM { 701 INT iTaskId; 702 CM_HAL_TASK_STATUS status; 703 UINT64 iTaskDuration; 704 LARGE_INTEGER iTaskGlobalCMSubmitTime; 705 LARGE_INTEGER iTaskCMSubmitTimeStamp; 706 LARGE_INTEGER iTaskHWStartTimeStamp; 707 LARGE_INTEGER iTaskHWEndTimeStamp; 708 LARGE_INTEGER iTaskCompleteTime; 709 } CM_HAL_QUERY_TASK_PARAM, *PCM_HAL_QUERY_TASK_PARAM; 710 711 typedef struct _CM_HAL_OSSYNC_PARAM { 712 HANDLE iOSSyncEvent; 713 } CM_HAL_OSSYNC_PARAM, *PCM_HAL_OSSYNC_PARAM; 714 715 typedef enum _CM_HAL_KERNEL_ARG_KIND { 716 CM_ARGUMENT_GENERAL = 0x0, 717 CM_ARGUMENT_SURFACE2D = 0x2, 718 CM_ARGUMENT_SURFACEBUFFER = 0x3, 719 CM_ARGUMENT_SURFACE3D = 0x4, 720 CM_ARGUMENT_SURFACE2D_UP = 0x7, 721 CM_ARGUMENT_SURFACE2D_DUAL = 0xa, 722 CM_ARGUMENT_SURFACE = 0xc, 723 CM_ARGUMENT_MAX = 0xe 724 } CM_HAL_KERNEL_ARG_KIND; 725 726 typedef struct _CM_HAL_KERNEL_ARG_PARAM { 727 CM_HAL_KERNEL_ARG_KIND Kind; 728 UINT iUnitCount; 729 UINT iUnitSize; 730 UINT iPayloadOffset; 731 BOOL bPerThread; 732 PBYTE pFirstValue; 733 UINT nCustomValue; 734 } CM_HAL_KERNEL_ARG_PARAM, *PCM_HAL_KERNEL_ARG_PARAM; 735 736 typedef struct _CM_HAL_INDIRECT_SURFACE { 737 WORD iKind; 738 WORD iSurfaceIndex; 739 WORD iBindingTableIndex; 740 } CM_HAL_INDIRECT_SURFACE, *PCM_HAL_INDIRECT_SURFACE; 741 742 typedef struct _CM_HAL_INDIRECT_DATA_PARAM { 743 WORD iIndirectDataSize; 744 WORD iSurfaceCount; 745 PBYTE pIndirectData; 746 PCM_INDIRECT_SURFACE_INFO pSurfaceInfo; 747 } CM_HAL_INDIRECT_DATA_PARAM, *PCM_HAL_INDIRECT_DATA_PARAM; 748 749 typedef enum _CM_GPUCOPY_KERNEL_ID { 750 GPU_COPY_KERNEL_UNKNOWN = 0x0, 751 752 GPU_COPY_KERNEL_GPU2CPU_UNALIGNED_NV12_ID = 0x1, 753 GPU_COPY_KERNEL_GPU2CPU_ALIGNED_NV12_ID = 0x2, 754 GPU_COPY_KERNEL_GPU2CPU_UNALIGNED_ID = 0x3, 755 GPU_COPY_KERNEL_GPU2CPU_ALIGNED_ID = 0x4, 756 757 GPU_COPY_KERNEL_CPU2GPU_NV12_ID = 0x5, 758 GPU_COPY_KERNEL_CPU2GPU_ID = 0x6, 759 760 GPU_COPY_KERNEL_GPU2GPU_NV12_ID = 0x7, 761 GPU_COPY_KERNEL_GPU2GPU_ID = 0x8, 762 763 GPU_COPY_KERNEL_CPU2CPU_ID = 0x9 764 } CM_GPUCOPY_KERNEL_ID; 765 766 typedef struct _CM_HAL_KERNEL_THREADSPACE_PARAM { 767 WORD iThreadSpaceWidth; 768 WORD iThreadSpaceHeight; 769 CM_HAL_DEPENDENCY_PATTERN patternType; 770 CM_HAL_DEPENDENCY dependencyInfo; 771 PCM_HAL_SCOREBOARD_XY_MASK pThreadCoordinates; 772 BYTE reuseBBUpdateMask; 773 CM_HAL_WAVEFRONT26Z_DISPATCH_INFO dispatchInfo; 774 BYTE globalDependencyMask; 775 BYTE walkingParamsValid; 776 CM_HAL_WALKING_PARAMETERS walkingParams; 777 BYTE dependencyVectorsValid; 778 CM_HAL_DEPENDENCY dependencyVectors; 779 CM_HAL_BB_DIRTY_STATUS BBdirtyStatus; 780 } CM_HAL_KERNEL_THREADSPACE_PARAM, *PCM_HAL_KERNEL_THREADSPACE_PARAM; 781 782 typedef struct _CM_HAL_WALKER_XY { 783 union { 784 struct { 785 DWORD x:16; 786 DWORD y:16; 787 }; 788 DWORD value; 789 }; 790 } CM_HAL_WALKER_XY, *PCM_HAL_WALKER_XY; 791 792 typedef struct _CM_HAL_WALKER_PARAMS { 793 DWORD InterfaceDescriptorOffset:5; 794 DWORD CmWalkerEnable:1; 795 DWORD ColorCountMinusOne:4; 796 DWORD ScoreboardMask:8; 797 DWORD MidLoopUnitX:2; 798 DWORD MidLoopUnitY:2; 799 DWORD MiddleLoopExtraSteps:5; 800 DWORD:5; 801 DWORD InlineDataLength; 802 PBYTE pInlineData; 803 CM_HAL_WALKER_XY LoopExecCount; 804 CM_HAL_WALKER_XY BlockResolution; 805 CM_HAL_WALKER_XY LocalStart; 806 CM_HAL_WALKER_XY LocalEnd; 807 CM_HAL_WALKER_XY LocalOutLoopStride; 808 CM_HAL_WALKER_XY LocalInnerLoopUnit; 809 CM_HAL_WALKER_XY GlobalResolution; 810 CM_HAL_WALKER_XY GlobalStart; 811 CM_HAL_WALKER_XY GlobalOutlerLoopStride; 812 CM_HAL_WALKER_XY GlobalInnerLoopUnit; 813 } CM_HAL_WALKER_PARAMS, *PCM_HAL_WALKER_PARAMS; 814 815 typedef struct _CM_GPGPU_WALKER_PARAMS { 816 DWORD InterfaceDescriptorOffset:5; 817 DWORD CmGpGpuEnable:1; 818 DWORD:26; 819 DWORD ThreadWidth; 820 DWORD ThreadHeight; 821 DWORD GroupWidth; 822 DWORD GroupHeight; 823 DWORD SLMSize; 824 } CM_GPGPU_WALKER_PARAMS, *PCM_GPGPU_WALKER_PARAMS; 825 826 typedef struct _CM_HAL_KERNEL_PARAM { 827 CM_HAL_KERNEL_ARG_PARAM CmArgParams[CM_MAX_ARGS_PER_KERNEL]; 828 PBYTE pKernelData; 829 PBYTE pKernelBinary; 830 UINT iKernelDataSize; 831 UINT iKernelBinarySize; 832 UINT iNumThreads; 833 UINT iNumArgs; 834 UINT iNumSurfaces; 835 UINT iPayloadSize; 836 UINT iKrnCurbeSize; 837 UINT iCurbeSizePerThread; 838 UINT iCrsThrdConstDataLn; 839 DWORD dwCmFlags; 840 UINT64 uiKernelId; 841 DWORD globalSurface[CM_MAX_GLOBAL_SURFACE_NUMBER]; 842 CM_HAL_INDIRECT_DATA_PARAM CmIndirectDataParam; 843 PBYTE pMovInsData; 844 UINT iMovInsDataSize; 845 CM_HAL_KERNEL_THREADSPACE_PARAM CmKernelThreadSpaceParam; 846 BOOL bGlobalSurfaceUsed; 847 CM_HAL_WALKER_PARAMS WalkerParams; 848 CM_GPGPU_WALKER_PARAMS GpGpuWalkerParams; 849 BOOL bKernelDebugEnabled; 850 BOOL bPerThreadArgExisted; 851 } CM_HAL_KERNEL_PARAM, *PCM_HAL_KERNEL_PARAM; 852 853 typedef enum _CM_HAL_MEMORY_OBJECT_CONTROL_G75 { 854 CM_MEMORY_OBJECT_CONTROL_USE_PTE = 0x0, 855 CM_MEMORY_OBJECT_CONTROL_UC = 0x2, 856 CM_MEMORY_OBJECT_CONTROL_LLC_ELLC_WB_CACHED = 0x4, 857 CM_MEMORY_OBJECT_CONTROL_ELLC_WB_CACHED = 0x6, 858 CM_MEMORY_OBJECT_CONTROL_L3_USE_PTE = 0x1, 859 CM_MEMORY_OBJECT_CONTROL_L3_UC = 0x3, 860 CM_MEMORY_OBJECT_CONTROL_L3_LLC_ELLC_WB_CACHED = 0x5, 861 CM_MEMORY_OBJECT_CONTROL_L3_ELLC_WB_CACHED = 0x7 862 } CM_HAL_MEMORY_OBJECT_CONTROL_G75; 863 864 typedef union _CM_HAL_MEMORY_OBJECT_CONTROL_G8 { 865 struct { 866 ULONG Age:2; 867 ULONG:1; 868 ULONG TargetCache:2; 869 ULONG CacheControl:2; 870 ULONG:25; 871 } Gen8; 872 873 ULONG DwordValue; 874 } CM_HAL_MEMORY_OBJECT_CONTROL_G8; 875 876 typedef struct _CM_HAL_TASK_PARAM { 877 UINT uiNumKernels; 878 UINT64 uiSyncBitmap; 879 UINT iBatchBufferSize; 880 DWORD dwVfeCurbeSize; 881 DWORD dwUrbEntrySize; 882 CM_HAL_SCOREBOARD_XY **ppThreadCoordinates; 883 CM_HAL_DEPENDENCY_PATTERN DependencyPattern; 884 UINT threadSpaceWidth; 885 UINT threadSpaceHeight; 886 UINT groupSpaceWidth; 887 UINT groupSpaceHeight; 888 UINT SLMSize; 889 CM_HAL_SURFACE_ENTRY_INFO_ARRAYS SurEntryInfoArrays; 890 UINT iCurKrnIndex; 891 UINT ColorCountMinusOne; 892 PCM_HAL_MASK_AND_RESET *ppDependencyMasks; 893 BYTE reuseBBUpdateMask; 894 UINT surfacePerBT; 895 BOOL blGpGpuWalkerEnabled; 896 CM_HAL_WALKING_PATTERN WalkingPattern; 897 UINT iPreemptionMode; 898 DWORD HasBarrier; 899 BYTE walkingParamsValid; 900 CM_HAL_WALKING_PARAMETERS walkingParams; 901 BYTE dependencyVectorsValid; 902 CM_HAL_DEPENDENCY dependencyVectors; 903 UINT KernelDebugEnabled; 904 } CM_HAL_TASK_PARAM; 905 906 typedef struct _CM_HAL_TASK_TIMESTAMP { 907 LARGE_INTEGER iGlobalCmSubmitTime[CM_MAXIMUM_TASKS]; 908 UINT64 iCMSubmitTimeStamp[CM_MAXIMUM_TASKS]; 909 LARGE_INTEGER iCompleteTime[CM_MAXIMUM_TASKS]; 910 } CM_HAL_TASK_TIMESTAMP; 911 912 typedef struct _CM_HAL_HINT_TASK_INDEXES { 913 UINT iKernelIndexes[CM_MAX_TASKS_EU_SATURATION]; 914 UINT iDispatchIndexes[CM_MAX_TASKS_EU_SATURATION]; 915 } CM_HAL_HINT_TASK_INDEXES; 916 917 typedef struct _CM_HAL_L3_CONFIG { 918 UINT L3_SQCREG1; 919 UINT L3_CNTLREG2; 920 UINT L3_CNTLREG3; 921 UINT L3_CNTLREG; 922 } CM_HAL_L3_CONFIG; 923 924 typedef struct _CM_HAL_INDEX_PARAM { 925 DWORD dwBTArray[8]; 926 } CM_HAL_INDEX_PARAM, *PCM_HAL_INDEX_PARAM; 927 928 typedef struct _CM_HAL_EXEC_TASK_PARAM { 929 PCM_HAL_KERNEL_PARAM *pKernels; 930 PUINT piKernelSizes; 931 UINT iNumKernels; 932 INT iTaskIdOut; 933 CM_HAL_SCOREBOARD_XY **ppThreadCoordinates; 934 CM_HAL_DEPENDENCY_PATTERN DependencyPattern; 935 UINT threadSpaceWidth; 936 UINT threadSpaceHeight; 937 CM_HAL_SURFACE_ENTRY_INFO_ARRAYS SurEntryInfoArrays; 938 PVOID OsData; 939 UINT ColorCountMinusOne; 940 PCM_HAL_MASK_AND_RESET *ppDependencyMasks; 941 UINT64 uiSyncBitmap; 942 BOOL bGlobalSurfaceUsed; 943 PUINT piKernelCurbeOffset; 944 CM_HAL_WALKING_PATTERN WalkingPattern; 945 BYTE walkingParamsValid; 946 CM_HAL_WALKING_PARAMETERS walkingParams; 947 BYTE dependencyVectorsValid; 948 CM_HAL_DEPENDENCY dependencyVectors; 949 BOOL bKernelDebugEnabled; 950 } CM_HAL_EXEC_TASK_PARAM, *PCM_HAL_EXEC_TASK_PARAM; 951 952 typedef struct _CM_HAL_POWER_OPTION_PARAM { 953 USHORT nSlice; 954 USHORT nSubSlice; 955 USHORT nEU; 956 } CM_HAL_POWER_OPTION_PARAM, *PCM_HAL_POWER_OPTION_PARAM; 957 958 typedef enum { 959 CM_KMD_ESCAPE_SET_FREQUENCY, 960 CM_KMD_ESCAPE_TURBO_SYNC 961 } CM_KMD_ESCAPE_CALL; 962 963 typedef enum { 964 UN_PREEMPTABLE_MODE, 965 COMMAND_BUFFER_MODE, 966 THREAD_GROUP_MODE, 967 MIDDLE_THREAD_MODE 968 } CM_HAL_PREEMPTION_MODE; 969 970 typedef enum _VA_CM_FORMAT { 971 972 VA_CM_FMT_UNKNOWN = 0, 973 974 VA_CM_FMT_BUFFER = 10, 975 VA_CM_FMT_A8R8G8B8 = 21, 976 VA_CM_FMT_X8R8G8B8 = 22, 977 VA_CM_FMT_A8 = 28, 978 VA_CM_FMT_A2B10G10R10 = 31, 979 VA_CM_FMT_A16B16G16R16 = 36, 980 VA_CM_FMT_P8 = 41, 981 VA_CM_FMT_L8 = 50, 982 VA_CM_FMT_A8L8 = 51, 983 VA_CM_FMT_R16U = 57, 984 VA_CM_FMT_V8U8 = 60, 985 VA_CM_FMT_R8U = 62, 986 VA_CM_FMT_D16 = 80, 987 VA_CM_FMT_L16 = 81, 988 VA_CM_FMT_A16B16G16R16F = 113, 989 VA_CM_FMT_R32F = 114, 990 VA_CM_FMT_NV12 = VA_FOURCC_NV12, 991 VA_CM_FMT_UYVY = VA_FOURCC_UYVY, 992 VA_CM_FMT_YUY2 = VA_FOURCC_YUY2, 993 VA_CM_FMT_444P = VA_FOURCC_444P, 994 VA_CM_FMT_411P = VA_FOURCC_411P, 995 VA_CM_FMT_422H = VA_FOURCC_422H, 996 VA_CM_FMT_422V = VA_FOURCC_422V, 997 VA_CM_FMT_IMC3 = VA_FOURCC_IMC3, 998 VA_CM_FMT_YV12 = VA_FOURCC_YV12, 999 1000 VA_CM_FMT_MAX = 0xFFFFFFFF 1001 } VA_CM_FORMAT; 1002 1003 #define CM_SURFACE_FORMAT VA_CM_FORMAT 1004 1005 #define CM_SURFACE_FORMAT_UNKNOWN VA_CM_FMT_UNKNOWN 1006 #define CM_SURFACE_FORMAT_A8R8G8B8 VA_CM_FMT_A8R8G8B8 1007 #define CM_SURFACE_FORMAT_X8R8G8B8 VA_CM_FMT_X8R8G8B8 1008 #define CM_SURFACE_FORMAT_A8 VA_CM_FMT_A8 1009 #define CM_SURFACE_FORMAT_P8 VA_CM_FMT_P8 1010 #define CM_SURFACE_FORMAT_R32F VA_CM_FMT_R32F 1011 #define CM_SURFACE_FORMAT_NV12 VA_CM_FMT_NV12 1012 #define CM_SURFACE_FORMAT_UYVY VA_CM_FMT_UYVY 1013 #define CM_SURFACE_FORMAT_YUY2 VA_CM_FMT_YUY2 1014 #define CM_SURFACE_FORMAT_V8U8 VA_CM_FMT_V8U8 1015 1016 #define CM_SURFACE_FORMAT_R8_UINT VA_CM_FMT_R8U 1017 #define CM_SURFACE_FORMAT_R16_UINT VA_CM_FMT_R16U 1018 #define CM_SURFACE_FORMAT_R16_SINT VA_CM_FMT_A8L8 1019 #define CM_SURFACE_FORMAT_D16 VA_CM_FMT_D16 1020 #define CM_SURFACE_FORMAT_L16 VA_CM_FMT_L16 1021 #define CM_SURFACE_FORMAT_A16B16G16R16 VA_CM_FMT_A16B16G16R16 1022 #define CM_SURFACE_FORMAT_R10G10B10A2 VA_CM_FMT_A2B10G10R10 1023 #define CM_SURFACE_FORMAT_A16B16G16R16F VA_CM_FMT_A16B16G16R16F 1024 1025 #define CM_SURFACE_FORMAT_444P VA_CM_FMT_444P 1026 #define CM_SURFACE_FORMAT_422H VA_CM_FMT_422H 1027 #define CM_SURFACE_FORMAT_422V VA_CM_FMT_422V 1028 #define CM_SURFACE_FORMAT_411P VA_CM_FMT_411P 1029 #define CM_SURFACE_FORMAT_IMC3 VA_CM_FMT_IMC3 1030 #define CM_SURFACE_FORMAT_YV12 VA_CM_FMT_YV12 1031 1032 #define CM_TEXTURE_ADDRESS_TYPE VACMTEXTUREADDRESS 1033 #define CM_TEXTURE_ADDRESS_WRAP VACMTADDRESS_WRAP 1034 #define CM_TEXTURE_ADDRESS_MIRROR VACMTADDRESS_MIRROR 1035 #define CM_TEXTURE_ADDRESS_CLAMP VACMTADDRESS_CLAMP 1036 #define CM_TEXTURE_ADDRESS_BORDER VACMTADDRESS_BORDER 1037 #define CM_TEXTURE_ADDRESS_MIRRORONCE VACMTADDRESS_MIRRORONCE 1038 1039 #define CM_TEXTURE_FILTER_TYPE VACMTEXTUREFILTERTYPE 1040 #define CM_TEXTURE_FILTER_TYPE_NONE VACMTEXF_NONE 1041 #define CM_TEXTURE_FILTER_TYPE_POINT VACMTEXF_POINT 1042 #define CM_TEXTURE_FILTER_TYPE_LINEAR VACMTEXF_LINEAR 1043 #define CM_TEXTURE_FILTER_TYPE_ANISOTROPIC VACMTEXF_ANISOTROPIC 1044 #define CM_TEXTURE_FILTER_TYPE_FLATCUBIC VACMTEXF_FLATCUBIC 1045 #define CM_TEXTURE_FILTER_TYPE_GAUSSIANCUBIC VACMTEXF_GAUSSIANCUBIC 1046 #define CM_TEXTURE_FILTER_TYPE_PYRAMIDALQUAD VACMTEXF_PYRAMIDALQUAD 1047 #define CM_TEXTURE_FILTER_TYPE_GAUSSIANQUAD VACMTEXF_GAUSSIANQUAD 1048 #define CM_TEXTURE_FILTER_TYPE_CONVOLUTIONMONO VACMTEXF_CONVOLUTIONMONO 1049 1050 typedef enum _DXVA_CM_QUERY_TYPE { 1051 DXVA_CM_QUERY_VERSION, 1052 DXVA_CM_QUERY_REG_HANDLE, 1053 DXVA_CM_MAX_VALUES, 1054 DXVA_CM_QUERY_GPU, 1055 DXVA_CM_QUERY_GT, 1056 DXVA_CM_MIN_RENDER_FREQ, 1057 DXVA_CM_MAX_RENDER_FREQ, 1058 DXVA_CM_QUERY_STEP, 1059 DXVA_CM_QUERY_GPU_FREQ, 1060 DXVA_CM_MAX_VALUES_EX, 1061 DXVA_CM_QUERY_SURFACE2D_FORMAT_COUNT, 1062 DXVA_CM_QUERY_SURFACE2D_FORMATS 1063 } DXVA_CM_QUERY_TYPE; 1064 1065 typedef struct _DXVA_CM_QUERY_CAPS { 1066 DXVA_CM_QUERY_TYPE Type; 1067 union { 1068 INT iVersion; 1069 HANDLE *hRegistration; 1070 CM_HAL_MAX_VALUES MaxValues; 1071 CM_HAL_MAX_VALUES_EX MaxValuesEx; 1072 UINT genCore; 1073 UINT genGT; 1074 UINT MinRenderFreq; 1075 UINT MaxRenderFreq; 1076 UINT genStepId; 1077 UINT GPUCurrentFreq; 1078 UINT Surface2DCount; 1079 CM_SURFACE_FORMAT *pSurface2DFormats; 1080 }; 1081 } DXVA_CM_QUERY_CAPS, *PDXVA_CM_QUERY_CAPS; 1082 1083 typedef struct _CmDriverContext_ { 1084 int deviceid; 1085 int device_rev; 1086 /* indicates whether the CreateBufferUp/CreateSurface2DUP is not supported */ 1087 int userptr_enabled; 1088 /* indicates whether CM uses the shared bufmgr or not 1089 * if it is zero, CM needs to initialize its own bufmgr. bufmgr is meaningless 1090 * If it is true, CM will share bufmgr with other components*/ 1091 int shared_bufmgr; 1092 dri_bufmgr *bufmgr; 1093 } CmDriverContext; 1094 1095 #define DRM_BO_FLINK 0x01 1096 #define DRM_BO_HANDLE 0x02 1097 1098 typedef struct _CmOsResource_ { 1099 VA_CM_FORMAT format; 1100 union { 1101 int aligned_width; 1102 int buf_bytes; 1103 }; 1104 int aligned_height; 1105 /* indicates whether it is BO_FLINK or BO_HANLDE */ 1106 int bo_flags; 1107 int bo_size; 1108 union { 1109 dri_bo *bo; 1110 UINT bo_flink; 1111 }; 1112 /* 1113 * the pitch/tile_type is only for 2D surface type. It should be ignored 1114 * for VA_CM_FORMAT_BUFFER. 1115 * pitch is in byte unit 1116 * And width/height is in pixel unit. 1117 */ 1118 int pitch; 1119 /* 1120 * It directly uses the I915_TILING_XX definition in i915_drm.h 1121 * I915_TILING_NONE 0 1122 * I915_TILING_X 1 1123 * I915_TILIGN_Y 2 1124 */ 1125 int tile_type; 1126 /* orig_width/height represents original width/height of 2D surface */ 1127 /* For the buffer type it can be ignored */ 1128 int orig_width, orig_height; 1129 } CmOsResource; 1130