1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Wei Lin<wei.w.lin@intel.com>
26 * Yuting Yang<yuting.yang@intel.com>
27 */
28
29 #pragma once
30
31 #include <assert.h>
32 #include <stdarg.h>
33 #include <stdio.h>
34 #include <iostream>
35 #include <exception>
36 #include <string.h>
37 #include <math.h>
38 #include "dlfcn.h"
39
40 #include "cm_debug.h"
41 #include "cm_csync.h"
42 #include "cm_common.h"
43
44 #ifdef __clang__
45 #define UNUSED_FIELD __attribute__((unused))
46 #else
47 #define UNUSED_FIELD
48 #endif
49
50 #define USERMODE_DEVICE_CONTEXT GENOS_CONTEXT
51
strtok_s(char * strToken,const char * strDelimit,char ** context)52 static inline char *strtok_s(char *strToken, const char *strDelimit,
53 char **context)
54 {
55 return strtok_r(strToken, strDelimit, context);
56 }
57
58 typedef unsigned char byte;
59
60 #define CM_1_0 100
61 #define CM_2_0 200
62 #define CM_2_1 201
63 #define CM_2_2 202
64 #define CM_2_3 203
65 #define CM_2_4 204
66 #define CM_3_0 300
67 #define CM_4_0 400
68 #define CM_5_0 500
69 #define CURRENT_CM_VERSION CM_5_0
70
71 #define MANVERSION 5
72 #define MANREVISION 0
73 #define SUBREVISION 0
74 #define BUILD_NUMBER 1001
75
76 #define CM_RT_API
77
78 #define CISA_MAGIC_NUMBER 0x41534943
79 #define CM_MIN_SURF_WIDTH 1
80 #define CM_MIN_SURF_HEIGHT 1
81 #define CM_MIN_SURF_DEPTH 2
82
83 #define CM_MAX_1D_SURF_WIDTH 0x8000000
84 #define CM_PAGE_ALIGNMENT 0x1000
85 #define CM_PAGE_ALIGNMENT_MASK 0x0FFF
86
87 #define CM_MAX_2D_SURF_WIDTH_IVB_PLUS 16384
88 #define CM_MAX_2D_SURF_HEIGHT_IVB_PLUS 16384
89
90 #define CM_INIT_PROGRAM_COUNT 16
91 #define CM_INIT_KERNEL_COUNT 64
92 #define CM_INIT_TASK_COUNT 16
93 #define CM_INIT_THREADGROUPSPACE_COUNT 8
94 #define CM_INIT_EVENT_COUNT 128
95 #define CM_INIT_THREADSPACE_COUNT 8
96
97 #define CM_NO_EVENT ((CmEvent *)(-1))
98
99 #define _NAME(...) #__VA_ARGS__
100 #define CM_MAX_OPTION_SIZE_IN_BYTE 512
101 #define CM_MAX_KERNEL_NAME_SIZE_IN_BYTE 256
102 #define CM_MAX_ISA_FILE_NAME_SIZE_IN_BYTE 256
103 #define CM_MAX_KERNEL_STRING_IN_BYTE 512
104
105 #define CM_MAX_TIMEOUT 2
106 #define CM_MAX_TIMEOUT_MS CM_MAX_TIMEOUT*1000
107
108 #define CM_INVALID_KERNEL_INDEX 0xFFFFFFFF
109 #define CM_INVALID_GLOBAL_SURFACE 0xFFFFFFFF
110
111 #define CM_MAX_ENTRY_FOR_A_SURFACE 6
112 #define CM_GTPIN_BUFFER_NUM 3
113
114 #define CM_INIT_KERNEL_PER_PROGRAM 64
115
116 #define CM_MAX_SURFACE2D_FORMAT_COUNT 17
117
118 #define CM_MAX_SURFACE2D_FORMAT_COUNT_INTERNAL 17
119
120 #define CM_MAX_SURFACE3D_FORMAT_COUNT 2
121
122 #define CM_RT_PLATFORM "CM_RT_PLATFORM"
123 #define INCLUDE_GTENVVAR_NAME "CM_DYNGT_INCLUDE"
124 #define CM_RT_SKU "CM_RT_SKU"
125 #define CM_RT_MAX_THREADS "CM_RT_MAX_THREADS"
126 #define CM_RT_AUB_PARAM "CM_RT_AUB_PARAM"
127 #define CM_RT_MUL_FRAME_FILE_BEGIN 0
128 #define CM_RT_MUL_FRAME_FILE_MIDDLE 1
129 #define CM_RT_MUL_FRAME_FILE_END 2
130 #define CM_RT_JITTER_DEBUG_FLAG "-debug"
131 #define CM_RT_JITTER_GTPIN_FLAG "-gtpin"
132 #define CM_RT_JITTER_GTPIN_NORESERVEREGS_FLAG "-gtpin_noreserve"
133 #define CM_RT_JITTER_NCSTATELESS_FLAG "-ncstateless"
134 #define CM_RT_JITTER_MAX_NUM_FLAGS 30
135 #define CM_RT_JITTER_NUM_RESERVED_FLAGS 3
136 #define CM_RT_JITTER_MAX_NUM_USER_FLAGS (CM_RT_JITTER_MAX_NUM_FLAGS - CM_RT_JITTER_NUM_RESERVED_FLAGS)
137
138 #define CM_RT_REGISTRY_FORCE_COHERENT_STATELESSBTI "ForceCoherentStatelessBTI"
139
140 #define CM_HAL_LOCKFLAG_READONLY 0x00000001
141 #define CM_HAL_LOCKFLAG_WRITEONLY 0x00000002
142
143 #define CM_MAX_DEPENDENCY_COUNT 8
144 #define CM_MAX_THREADSPACE_WIDTH 511
145 #define CM_MAX_THREADSPACE_HEIGHT 511
146 #define CM_MAX_THREADSPACE_WIDTH_SKLUP 2047
147 #define CM_MAX_THREADSPACE_HEIGHT_SKLUP 2047
148
149 #define MAX_SLM_SIZE_PER_GROUP_IN_1K 64
150 #define CM_MAX_THREAD_GROUP 64
151
152 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_2 1
153 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_2_1 5
154 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_3_1 6
155
156 #define CM_FLAG_CURBE_ENABLED 0x00000001
157 #define CM_FLAG_NONSTALLING_SCOREBOARD_ENABLED 0x00000002
158
159 #define GT_PIN_MSG_SIZE 1024
160
161 #define CM_GLOBAL_SURFACE_NUMBER 4
162
163 #define GT_RESERVED_INDEX_START 250
164 #define GT_RESERVED_INDEX_START_GEN9_PLUS 240
165 #define CM_GLOBAL_SURFACE_INDEX_START 243
166 #define CM_GLOBAL_SURFACE_INDEX_START_GEN9_PLUS 1
167 #define CM_NULL_SURFACE_BINDING_INDEX 0
168
169 #define CM_NULL_SURFACE 0xFFFF
170
171 #define R64_OFFSET 32*64
172 #define CM_MOVE_INSTRUCTION_SIZE 16
173
174 #define CM_IVB_HSW_ADJUST_Y_SCOREBOARD_DW0 0x00000040
175 #define CM_IVB_HSW_ADJUST_Y_SCOREBOARD_DW1 0x20063d29
176 #define CM_IVB_HSW_ADJUST_Y_SCOREBOARD_DW2 0x00000006
177
178 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW0 0x00000040
179 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW1 0x20061248
180 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW2 0x1e000006
181
182 #define CM_MINIMUM_NUM_KERNELS_ENQWHINTS 2
183
184 #define CM_THREADSPACE_MAX_COLOR_COUNT 16
185 #define CM_INVALID_COLOR_COUNT 0
186
187 #define CM_KERNEL_DATA_CLEAN 0
188 #define CM_KERNEL_DATA_KERNEL_ARG_DIRTY 1
189 #define CM_KERNEL_DATA_THREAD_ARG_DIRTY (1 << 1)
190 #define CM_KERNEL_DATA_PAYLOAD_DATA_DIRTY (1 << 2)
191 #define CM_KERNEL_DATA_PAYLOAD_DATA_SIZE_DIRTY (1 << 3)
192 #define CM_KERNEL_DATA_GLOBAL_SURFACE_DIRTY (1 << 4)
193 #define CM_KERNEL_DATA_THREAD_COUNT_DIRTY (1 << 5)
194
195 #define SIWA_ONLY_A0 0x0fff0001u
196 #define SIWA_ONLY_A1 0x0fff0002u
197 #define SIWA_ONLY_A2 0x0fff0004u
198 #define SIWA_ONLY_A3 0x0fff0008u
199 #define SIWA_ONLY_A4 0x0fff0010u
200 #define SIWA_ONLY_A5 0x0fff0020u
201 #define SIWA_ONLY_A6 0x0fff0040u
202 #define SIWA_ONLY_A7 0x0fff0080u
203 #define SIWA_ONLY_A8 0x0fff0100u
204 #define SIWA_ONLY_A9 0x0fff0200u
205 #define SIWA_ONLY_AA 0x0fff0400u
206 #define SIWA_ONLY_AB 0x0fff0800u
207 #define SIWA_ONLY_AC 0x0fff1000u
208
209 typedef enum _GPU_PLATFORM {
210 PLATFORM_INTEL_UNKNOWN = 0,
211 PLATFORM_INTEL_SNB = 1,
212 PLATFORM_INTEL_IVB = 2,
213 PLATFORM_INTEL_HSW = 3,
214 PLATFORM_INTEL_BDW = 4,
215 PLATFORM_INTEL_CHV = 6,
216 PLATFORM_INTEL_SKL = 7,
217 PLATFORM_INTEL_BXT = 8,
218 PLATFORM_INTEL_TOTAL
219 } GPU_PLATFORM;
220
221 typedef enum _GPU_GT_PLATFORM {
222 PLATFORM_INTEL_GT_UNKNOWN = 0,
223 PLATFORM_INTEL_GT1 = 1,
224 PLATFORM_INTEL_GT2 = 2,
225 PLATFORM_INTEL_GT3 = 3,
226 PLATFORM_INTEL_GT4 = 4,
227 PLATFORM_INTEL_GTCHV = 7,
228 PLATFORM_INTEL_GTA = 8,
229 PLATFORM_INTEL_GTC = 9,
230 PLATFORM_INTEL_GT1_5 = 10,
231 PLATFORM_INTEL_GTX = 11,
232
233 PLATFORM_INTEL_GT_TOTAL
234 } GPU_GT_PLATFORM;
235
236 typedef enum _CM_DEVICE_CAP_NAME
237 {
238 CAP_KERNEL_COUNT_PER_TASK,
239 CAP_KERNEL_BINARY_SIZE,
240 CAP_SAMPLER_COUNT ,
241 CAP_SAMPLER_COUNT_PER_KERNEL,
242 CAP_BUFFER_COUNT ,
243 CAP_SURFACE2D_COUNT,
244 CAP_SURFACE3D_COUNT,
245 CAP_SURFACE_COUNT_PER_KERNEL,
246 CAP_ARG_COUNT_PER_KERNEL,
247 CAP_ARG_SIZE_PER_KERNEL ,
248 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK,
249 CAP_HW_THREAD_COUNT,
250 CAP_SURFACE2D_FORMAT_COUNT,
251 CAP_SURFACE2D_FORMATS,
252 CAP_SURFACE3D_FORMAT_COUNT,
253 CAP_SURFACE3D_FORMATS,
254 CAP_VME_STATE_G6_COUNT,
255 CAP_GPU_PLATFORM,
256 CAP_GT_PLATFORM,
257 CAP_MIN_FREQUENCY,
258 CAP_MAX_FREQUENCY,
259 CAP_L3_CONFIG,
260 CAP_GPU_CURRENT_FREQUENCY,
261 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK_NO_THREAD_ARG,
262 CAP_USER_DEFINED_THREAD_COUNT_PER_MEDIA_WALKER,
263 CAP_USER_DEFINED_THREAD_COUNT_PER_THREAD_GROUP
264 } CM_DEVICE_CAP_NAME;
265
266 #define HW_GT_STEPPING_A0 "A0"
267 #define HW_GT_STEPPING_A1 "A1"
268 #define HW_GT_STEPPING_B0 "B0"
269 #define HW_GT_STEPPING_C0 "C0"
270 #define HW_GT_STEPPING_D0 "D0"
271
272 typedef enum _SURFACE_DESTROY_KIND {
273 APP_DESTROY = 0,
274 GC_DESTROY = 1,
275 FORCE_DESTROY = 2,
276 DELAYED_DESTROY = 3
277 } SURFACE_DESTROY_KIND;
278
279 typedef enum _CM_GPUCOPY_DIRECTION {
280 CM_FASTCOPY_GPU2CPU = 0,
281 CM_FASTCOPY_CPU2GPU = 1,
282 CM_FASTCOPY_GPU2GPU = 2,
283 CM_FASTCOPY_CPU2CPU = 3
284 } CM_GPUCOPY_DIRECTION;
285
286 typedef enum _CM_FASTCOPY_OPTION {
287 CM_FASTCOPY_OPTION_NONBLOCKING = 0x00,
288 CM_FASTCOPY_OPTION_BLOCKING = 0x01
289 } CM_FASTCOPY_OPTION;
290
291 typedef enum _CM_STATUS {
292 CM_STATUS_QUEUED = 0,
293 CM_STATUS_FLUSHED = 1,
294 CM_STATUS_FINISHED = 2,
295 CM_STATUS_STARTED = 3
296 } CM_STATUS;
297
298 typedef struct _CM_DLL_FILE_VERSION
299 {
300 WORD wMANVERSION;
301 WORD wMANREVISION;
302 WORD wSUBREVISION;
303 WORD wBUILD_NUMBER;
304 } CM_DLL_FILE_VERSION, *PCM_DLL_FILE_VERSION;
305
306 typedef enum _CM_TS_FLAG {
307 WHITE = 0,
308 GRAY = 1,
309 BLACK = 2
310 } CM_TS_FLAG;
311
312 typedef struct _CM_COORDINATE {
313 INT x;
314 INT y;
315 } CM_COORDINATE, *PCM_COORDINATE;
316
317 typedef struct _CM_THREAD_SPACE_UNIT {
318 PVOID pKernel;
319 UINT threadId;
320 INT numEdges;
321 CM_COORDINATE scoreboardCoordinates;
322 BYTE dependencyMask;
323 BYTE reset;
324 } CM_THREAD_SPACE_UNIT;
325
326 typedef enum _CM_THREAD_SPACE_DIRTY_STATUS {
327 CM_THREAD_SPACE_CLEAN = 0,
328 CM_THREAD_SPACE_DEPENDENCY_MASK_DIRTY = 1,
329 CM_THREAD_SPACE_DATA_DIRTY = 2
330 } CM_THREAD_SPACE_DIRTY_STATUS, *PCM_THREAD_SPACE_DIRTY_STATUS;
331
332 typedef struct _CM_DEPENDENCY {
333 UINT count;
334 INT deltaX[CM_MAX_DEPENDENCY_COUNT];
335 INT deltaY[CM_MAX_DEPENDENCY_COUNT];
336 } CM_DEPENDENCY;
337
338 typedef enum _CM_INTERNAL_TASK_TYPE {
339 CM_INTERNAL_TASK_WITH_THREADSPACE,
340 CM_INTERNAL_TASK_WITH_THREADGROUPSPACE,
341 CM_INTERNAL_TASK_ENQUEUEWITHHINTS
342 } CM_INTERNAL_TASK_TYPE;
343
344 #define CM_TASK_TYPE_DEFAULT CM_INTERNAL_TASK_WITH_THREADSPACE
345
346 typedef enum _MEMORY_OBJECT_CONTROL {
347 MEMORY_OBJECT_CONTROL_USE_GTT_ENTRY,
348 MEMORY_OBJECT_CONTROL_FROM_GTT_ENTRY =
349 MEMORY_OBJECT_CONTROL_USE_GTT_ENTRY,
350
351 MEMORY_OBJECT_CONTROL_USE_PTE = MEMORY_OBJECT_CONTROL_FROM_GTT_ENTRY,
352 MEMORY_OBJECT_CONTROL_L3_USE_PTE,
353 MEMORY_OBJECT_CONTROL_UC,
354 MEMORY_OBJECT_CONTROL_L3_UC,
355 MEMORY_OBJECT_CONTROL_LLC_ELLC,
356 MEMORY_OBJECT_CONTROL_L3_LLC_ELLC,
357 MEMORY_OBJECT_CONTROL_ELLC,
358 MEMORY_OBJECT_CONTROL_L3_ELLC,
359
360 MEMORY_OBJECT_CONTROL_BDW_ELLC_ONLY = 0,
361 MEMORY_OBJECT_CONTROL_BDW_LLC_ONLY,
362 MEMORY_OBJECT_CONTROL_BDW_LLC_ELLC_ALLOWED,
363 MEMORY_OBJECT_CONTROL_BDW_L3_LLC_ELLC_ALLOWED,
364
365 MEMORY_OBJECT_CONTROL_UNKNOW = 0xff
366 } MEMORY_OBJECT_CONTROL;
367
368 typedef enum _MEMORY_TYPE {
369 CM_USE_PTE,
370 CM_UN_CACHEABLE,
371 CM_WRITE_THROUGH,
372 CM_WRITE_BACK,
373
374 MEMORY_TYPE_BDW_UC_WITH_FENCE = 0,
375 MEMORY_TYPE_BDW_UC,
376 MEMORY_TYPE_BDW_WT,
377 MEMORY_TYPE_BDW_WB
378 } MEMORY_TYPE;
379
380 typedef struct _CM_SURFACE_MEM_OBJ_CTRL {
381 MEMORY_OBJECT_CONTROL mem_ctrl;
382 MEMORY_TYPE mem_type;
383 INT age;
384 } CM_SURFACE_MEM_OBJ_CTRL;
385
386 #define SKL_L3_CONFIG_NUM 8
387 #define CHV_L3_CONFIG_NUM 8
388 #define BDW_L3_CONFIG_NUM 8
389 #define HSW_L3_CONFIG_NUM 12
390 #define IVB_2_L3_CONFIG_NUM 12
391 #define IVB_1_L3_CONFIG_NUM 12
392
393 typedef struct _L3_CONFIG_REGISTER_VALUES{
394 UINT SQCREG1_VALUE;
395 UINT CNTLREG2_VALUE;
396 UINT CNTLREG3_VALUE;
397 UINT CNTLREG_VALUE;
398 } L3_CONFIG_REGISTER_VALUES;
399
400 typedef enum _L3_SUGGEST_CONFIG
401 {
402 IVB_L3_PLANE_DEFAULT,
403 IVB_L3_PLANE_1,
404 IVB_L3_PLANE_2,
405 IVB_L3_PLANE_3,
406 IVB_L3_PLANE_4,
407 IVB_L3_PLANE_5,
408 IVB_L3_PLANE_6,
409 IVB_L3_PLANE_7,
410 IVB_L3_PLANE_8,
411 IVB_L3_PLANE_9,
412 IVB_L3_PLANE_10,
413 IVB_L3_PLANE_11,
414
415 HSW_L3_PLANE_DEFAULT = IVB_L3_PLANE_DEFAULT,
416 HSW_L3_PLANE_1,
417 HSW_L3_PLANE_2,
418 HSW_L3_PLANE_3,
419 HSW_L3_PLANE_4,
420 HSW_L3_PLANE_5,
421 HSW_L3_PLANE_6,
422 HSW_L3_PLANE_7,
423 HSW_L3_PLANE_8,
424 HSW_L3_PLANE_9,
425 HSW_L3_PLANE_10,
426 HSW_L3_PLANE_11,
427
428 BDW_L3_PLANE_DEFAULT = IVB_L3_PLANE_DEFAULT,
429 BDW_L3_PLANE_1,
430 BDW_L3_PLANE_2,
431 BDW_L3_PLANE_3,
432 BDW_L3_PLANE_4,
433 BDW_L3_PLANE_5,
434 BDW_L3_PLANE_6,
435 BDW_L3_PLANE_7,
436
437 CHV_L3_PLANE_DEFAULT = IVB_L3_PLANE_DEFAULT,
438 CHV_L3_PLANE_1,
439 CHV_L3_PLANE_2,
440 CHV_L3_PLANE_3,
441 CHV_L3_PLANE_4,
442 CHV_L3_PLANE_5,
443 CHV_L3_PLANE_6,
444 CHV_L3_PLANE_7,
445
446 SKL_L3_PLANE_DEFAULT = IVB_L3_PLANE_DEFAULT,
447 SKL_L3_PLANE_1,
448 SKL_L3_PLANE_2,
449 SKL_L3_PLANE_3,
450 SKL_L3_PLANE_4,
451 SKL_L3_PLANE_5,
452 SKL_L3_PLANE_6,
453 SKL_L3_PLANE_7,
454
455 IVB_SLM_PLANE_DEFAULT = IVB_L3_PLANE_9,
456 HSW_SLM_PLANE_DEFAULT = HSW_L3_PLANE_9,
457 BDW_SLM_PLANE_DEFAULT = BDW_L3_PLANE_5,
458 CHV_SLM_PLANE_DEFAULT = CHV_L3_PLANE_5
459 } L3_SUGGEST_CONFIG;
460
461 static const L3_CONFIG_REGISTER_VALUES IVB_L3_PLANE[ IVB_1_L3_CONFIG_NUM ] =
462 {
463 { 0x01730000, 0x00080040, 0x00000000 },
464 { 0x00730000, 0x02040040, 0x00000000 },
465 { 0x00730000, 0x00800040, 0x00080410 },
466 { 0x00730000, 0x01000038, 0x00080410 },
467 { 0x00730000, 0x02000038, 0x00040410 },
468 { 0x00730000, 0x01000038, 0x00040420 },
469 { 0x01730000, 0x00000038, 0x00080420 },
470 { 0x01730000, 0x00000040, 0x00080020 },
471 { 0x00730000, 0x020400a1, 0x00000000 },
472 { 0x00730000, 0x010000a1, 0x00040810 },
473 { 0x00730000, 0x008000a1, 0x00080410 },
474 { 0x00730000, 0x008000a1, 0x00040420 }
475 };
476
477 static const L3_CONFIG_REGISTER_VALUES HSW_L3_PLANE[ HSW_L3_CONFIG_NUM ] =
478 {
479 { 0x01610000, 0x00080040, 0x00000000 },
480 { 0x00610000, 0x02040040, 0x00000000 },
481 { 0x00610000, 0x00800040, 0x00080410 },
482 { 0x00610000, 0x01000038, 0x00080410 },
483 { 0x00610000, 0x02000038, 0x00040410 },
484 { 0x00610000, 0x01000038, 0x00040420 },
485 { 0x01610000, 0x00000038, 0x00080420 },
486 { 0x01610000, 0x00000040, 0x00080020 },
487 { 0x00610000, 0x020400a1, 0x00000000 },
488 { 0x00610000, 0x010000a1, 0x00040810 },
489 { 0x00610000, 0x008000a1, 0x00080410 },
490 { 0x00610000, 0x008000a1, 0x00040420 }
491 };
492
493 static const L3_CONFIG_REGISTER_VALUES BDW_L3_PLANE[ BDW_L3_CONFIG_NUM ] =
494 {
495 { 0, 0, 0, 0x60000060 },
496 { 0, 0, 0, 0x00410060 },
497 { 0, 0, 0, 0x00418040 },
498 { 0, 0, 0, 0x00020040 },
499 { 0, 0, 0, 0x80000040 },
500 { 0, 0, 0, 0x60000021 },
501 { 0, 0, 0, 0x00410021 },
502 { 0, 0, 0, 0x00808021 }
503 };
504
505 static const L3_CONFIG_REGISTER_VALUES CHV_L3_PLANE[ CHV_L3_CONFIG_NUM ] =
506 {
507 { 0, 0, 0, 0x60000060 },
508 { 0, 0, 0, 0x00410060 },
509 { 0, 0, 0, 0x00418040 },
510 { 0, 0, 0, 0x00020040 },
511 { 0, 0, 0, 0x80000040 },
512 { 0, 0, 0, 0x60000021 },
513 { 0, 0, 0, 0x00410021 },
514 { 0, 0, 0, 0x00808021 }
515 };
516
517 static const L3_CONFIG_REGISTER_VALUES SKL_L3_PLANE[SKL_L3_CONFIG_NUM] =
518 {
519 { 0x60000060, 0x00000000, 0x00000000 },
520 { 0x00808060, 0x00000000, 0x00000000 },
521 { 0x00818040, 0x00000000, 0x00000000 },
522 { 0x00030040, 0x00000000, 0x00000000 },
523 { 0x80000040, 0x00000000, 0x00000000 },
524 { 0x60000121, 0x00000000, 0x00000000 },
525 { 0x00410121, 0x00000000, 0x00000000 },
526 { 0x00808121, 0x00000000, 0x00000000 }
527 };
528
529 typedef struct _DXVA_CM_SET_CAPS {
530 DXVA_CM_SET_TYPE Type;
531 union
532 {
533 UINT MaxValue;
534 struct
535 {
536 UINT L3_SQCREG1;
537 UINT L3_CNTLREG2;
538 UINT L3_CNTLREG3;
539 UINT L3_CNTLREG;
540 };
541 };
542 } DXVA_CM_SET_CAPS, *PDXVA_CM_SET_CAPS;
543
544 typedef struct _CM_HAL_EXEC_GROUPED_TASK_PARAM {
545 PVOID *pKernels;
546 PUINT piKernelSizes;
547 UINT iNumKernels;
548 INT iTaskIdOut;
549 UINT threadSpaceWidth;
550 UINT threadSpaceHeight;
551 UINT groupSpaceWidth;
552 UINT groupSpaceHeight;
553 UINT iSLMSize;
554 } CM_HAL_EXEC_GROUPED_TASK_PARAM, *PCM_HAL_EXEC_GROUPED_TASK_PARAM;
555
556 typedef enum _CM_ARG_KIND {
557 ARG_KIND_GENERAL = 0x0,
558 ARG_KIND_SURFACE_2D = 0x2,
559 ARG_KIND_SURFACE_1D = 0x3,
560 ARG_KIND_SURFACE_2D_UP = 0x7,
561 ARG_KIND_SURFACE_2D_DUAL = 0xa,
562 ARG_KIND_SURFACE = 0xc,
563 } CM_ARG_KIND;
564
565 typedef enum _SURFACE_KIND {
566 DATA_PORT_SURF,
567 DUAL_SURF
568 } SURFACE_KIND;
569
570 typedef struct _CM_ARG {
571 WORD unitKind;
572 WORD unitKindOrig;
573
574 WORD index;
575 SURFACE_KIND s_k;
576
577 UINT unitCount;
578
579 WORD unitSize;
580 WORD unitSizeOrig;
581
582 WORD unitOffsetInPayload;
583 WORD unitOffsetInPayloadOrig;
584 BOOL bIsDirty;
585 BOOL bIsSet;
586 UINT nCustomValue;
587
588 union {
589 BYTE *pValue;
590 INT *pIValue;
591 UINT *pUIValue;
592 FLOAT *pFValue;
593 };
594
595 WORD *surfIndex;
596
_CM_ARG_CM_ARG597 _CM_ARG() {
598 unitKind = 0;
599 unitCount = 0;
600 unitSize = 0;
601 unitOffsetInPayload = 0;
602 pValue = NULL;
603 bIsDirty = FALSE;
604 }} CM_ARG;
605
606 #define CM_JIT_FLAG_SIZE 256
607 #define CM_JIT_ERROR_MESSAGE_SIZE 512
608 #define CM_JIT_PROF_INFO_SIZE 4096
609 #define CM_PROFILE_KIND_DUAL_2D_SURFACE_STATES 0
610
611 typedef struct _CM_PROFILE_INFO {
612 int kind;
613 int index;
614 int value;
615 } CM_PROFILE_INFO;
616
617 typedef struct _CM_JIT_INFO {
618 bool isSpill;
619 int numGRFUsed;
620 int numAsmCount;
621
622 unsigned int spillMemUsed;
623 void *genDebugInfo;
624 unsigned int genDebugInfoSize;
625 } CM_JIT_INFO;
626
627 typedef struct {
628 unsigned short name_index;
629 unsigned char size;
630 unsigned char *values;
631 char *name;
632 } attribute_info_t;
633
634 typedef struct {
635 unsigned short name_index;
636 unsigned char bit_properties;
637 unsigned short num_elements;
638 unsigned short alias_index;
639 unsigned short alias_offset;
640 unsigned char attribute_count;
641 attribute_info_t *attributes;
642 } gen_var_info_t;
643
644 typedef struct {
645 unsigned short name_index;
646 unsigned short num_elements;
647 unsigned char attribute_count;
648 attribute_info_t *attributes;
649 } spec_var_info_t;
650
651 typedef struct {
652 unsigned short name_index;
653 unsigned char kind;
654 unsigned char attribute_count;
655 attribute_info_t *attributes;
656 } label_info_t;
657
658 typedef struct _CM_KERNEL_INFO {
659 char kernelName[CM_MAX_KERNEL_NAME_SIZE_IN_BYTE];
660 UINT inputCountOffset;
661
662 UINT kernelIsaOffset;
663 UINT kernelIsaSize;
664
665 union {
666 UINT jitBinarySize;
667 UINT genxBinarySize;
668 };
669
670 union {
671 void *jitBinaryCode;
672 UINT genxBinaryOffset;
673 };
674
675 void *pOrigBinary;
676 UINT uiOrigBinarySize;
677
678 unsigned short globalStringCount;
679 const char **globalStrings;
680 char kernelASMName[CM_MAX_KERNEL_NAME_SIZE_IN_BYTE + 1];
681 BYTE kernelSLMSize;
682
683 CM_JIT_INFO *jitInfo;
684
685 UINT variable_count;
686 gen_var_info_t *variables;
687 UINT address_count;
688 spec_var_info_t *address;
689 UINT predicte_count;
690 spec_var_info_t *predictes;
691 UINT label_count;
692 label_info_t *label;
693 UINT surface_count;
694 spec_var_info_t *surface;
695
696 UINT kernelInfoRefCount;
697 } CM_KERNEL_INFO;
698
699 #define NUM_SEARCH_PATH_STATES_G6 14
700 #define NUM_MBMODE_SETS_G6 4
701
702 typedef struct _CM_ARG_64 {
703 void *pValue;
704 int size;
705 } CM_ARG_64;
706
707 typedef enum _CM_MESSAGE_SEQUENCE_ {
708 CM_MS_1x1 = 0,
709 CM_MS_16x1 = 1,
710 CM_MS_16x4 = 2,
711 CM_MS_32x1 = 3,
712 CM_MS_32x4 = 4,
713 CM_MS_64x1 = 5,
714 CM_MS_64x4 = 6
715 } CM_MESSAGE_SEQUENCE;
716
717 typedef enum _CM_MIN_MAX_FILTER_CONTROL_ {
718 CM_MIN_FILTER = 0,
719 CM_MAX_FILTER = 1,
720 CM_BOTH_FILTER = 3
721 } CM_MIN_MAX_FILTER_CONTROL;
722
723 typedef enum _CM_VA_FUNCTION_ {
724 CM_VA_MINMAXFILTER = 0,
725 CM_VA_DILATE = 1,
726 CM_VA_ERODE = 2
727 } CM_VA_FUNCTION;
728
729 typedef enum _CM_SURFACE_ADDRESS_CONTROL_MODE_ {
730 CM_SURFACE_CLAMP = 0,
731 CM_SURFACE_MIRROR = 1
732 } CM_SURFACE_ADDRESS_CONTROL_MODE;
733
734 typedef enum _GFX_TEXTUREFILTERTYPE GFX_TEXTUREFILTERTYPE;
735
736 static const CM_HAL_POWER_OPTION_PARAM
737 CM_PLATFORM_POWER_CONFIGURATION[PLATFORM_INTEL_TOTAL]
738 [PLATFORM_INTEL_GT_TOTAL] = {
739 {
740 0},
741
742 {
743 {0},
744 {1, 1, 10},
745 {1, 2, 20},
746 {2, 4, 40}
747 },
748
749 {
750 {0},
751 {1, 2, 12},
752 {1, 3, 23},
753 {2, 6, 47}
754 },
755
756 {
757 0},
758
759 {
760 0}
761 };
762
763 typedef int (*pJITCompile) (const char *kernelName,
764 const void *kernelIsa,
765 UINT kernelIsaSize,
766 void *&genBinary,
767 UINT & genBinarySize,
768 const char *platform,
769 int majorVersion,
770 int minorVersion,
771 int numArgs,
772 const char *args[],
773 char *errorMsg, CM_JIT_INFO * jitInfo);
774 typedef int (*pJITCompileSim) (const char *kernelName,
775 const void *kernelIsa,
776 UINT kernelIsaSize,
777 const char *asmFileName,
778 const char *platform,
779 int majorVersion,
780 int minorVersion,
781 int numArgs,
782 const char *args[],
783 char *errorMsg, CM_JIT_INFO * jitInfo);
784 typedef void (*pFreeBlock) (void *);
785 typedef void (*pJITVersion) (unsigned int &majorV, unsigned int &minorV);
786
787 #define JITCOMPILE_FUNCTION_STR "JITCompile"
788 #define JITCOMPILESIM_FUNCTION_STR "JITCompileSim"
789 #define FREEBLOCK_FUNCTION_STR "freeBlock"
790 #define JITVERSION_FUNCTION_STR "getJITVersion"
791
792 typedef enum _JITDLL_FUNCTION_ORDINAL_ {
793 JITDLL_ORDINAL_JITCOMPILE = 1,
794 JITDLL_ORDINAL_JITCOMPILESIM = 2,
795 JITDLL_ORDINAL_FREEBLOCK = 3,
796 JITDLL_ORDINAL_JITVERSION = 4
797 } JITDLL_FUNCTION_ORDINAL;
798
799 typedef enum _CM_ENUM_CLASS_TYPE {
800 CM_ENUM_CLASS_TYPE_CMBUFFER_RT = 0,
801 CM_ENUM_CLASS_TYPE_CMSURFACE2D = 1,
802 CM_ENUM_CLASS_TYPE_CMSURFACE2DUP = 2,
803 } CM_ENUM_CLASS_TYPE;
804
805 class SurfaceIndex {
806 public:
SurfaceIndex()807 SurfaceIndex() {
808 index = 0;
809 };
SurfaceIndex(const SurfaceIndex & _src)810 SurfaceIndex(const SurfaceIndex & _src) {
811 index = _src.index;
812 };
SurfaceIndex(const unsigned int & _n)813 SurfaceIndex(const unsigned int &_n) {
814 index = _n;
815 };
816 SurfaceIndex & operator =(const unsigned int &_n) {
817 this->index = _n;
818 return *this;
819 };
820 SurfaceIndex & operator +(const unsigned int &_n) {
821 this->index += _n;
822 return *this;
823 };
get_data(void)824 unsigned int get_data(void) {
825 return index;
826 };
827 private:
828 // TODO Remove this placeholder once the offload lib is updated.
829 void *vptr_placeholder UNUSED_FIELD;
830 unsigned int index;
831 unsigned char extra_byte UNUSED_FIELD;
832 };
833
834 typedef enum _CM_KERNEL_INTERNAL_ARG_TYPE {
835 CM_KERNEL_INTERNEL_ARG_PERKERNEL = 0,
836 CM_KERNEL_INTERNEL_ARG_PERTHREAD = 1
837 } CM_KERNEL_INTERNAL_ARG_TYPE, *PCM_KERNEL_INTERNAL_ARG_TYPE;
838
839 typedef struct _CM_CONTEXT {
840 GENOS_CONTEXT GenHwDrvCtx;
841 union {
842 PVOID pCmHal;
843 PCM_HAL_STATE pCmHalState;
844 };
845 } CM_CONTEXT, *PCM_CONTEXT;
846