1 /*
2  * Copyright � 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *     Wei Lin<wei.w.lin@intel.com>
26  *     Yuting Yang<yuting.yang@intel.com>
27  */
28 
29 #ifndef __GENHW_HW_H__
30 #define __GENHW_HW_H__
31 
32 #include "os_interface.h"
33 #include "hw_cmd.h"
34 #include "hw_cmd_g9.h"
35 #include "gen_hw.h"
36 
37 #define GENHW_PAGE_SIZE         0x1000
38 
39 #define GENHW_YTILE_H_ALIGNMENT  32
40 #define GENHW_YTILE_W_ALIGNMENT  128
41 #define GENHW_XTILE_H_ALIGNMENT  8
42 #define GENHW_XTILE_W_ALIGNMENT  512
43 
44 #define GENHW_YTILE_H_SHIFTBITS  5
45 #define GENHW_YTILE_W_SHIFTBITS  7
46 #define GENHW_XTILE_H_SHITFBITS  3
47 #define GENHW_XTILE_W_SHIFTBITS  9
48 
49 #define GENHW_MACROBLOCK_SIZE   16
50 
51 #define GFX_MASK(lo,hi)          ((1UL << (hi)) |    \
52                                  ((1UL << (hi)) -    \
53                                   (1UL << (lo))))
54 
55 #define GFX_MIN(a,b)             (((a) < (b)) ? (a) : (b))
56 #define GFX_MAX(a,b)             (((a) > (b)) ? (a) : (b))
57 
58 #define GFX_CLAMP_MIN_MAX(a,min,max)   ((a) < (min) ? (min) : GFX_MIN ((a), (max)))
59 
60 #define GENHW_KERNEL_LOAD_FAIL  -1
61 
62 #define GENHW_MAX_SURFACE_PLANES    3
63 
64 #define GENHW_KERNEL_ALLOCATION_FREE    0
65 #define GENHW_KERNEL_ALLOCATION_USED    1
66 #define GENHW_KERNEL_ALLOCATION_LOCKED  2
67 
68 #define GENHW_SSH_INSTANCES            16
69 #define GENHW_SSH_INSTANCES_MAX        64
70 
71 #define GENHW_SSH_BINDING_TABLES        1
72 #define GENHW_SSH_BINDING_TABLES_MIN    1
73 #define GENHW_SSH_BINDING_TABLES_MAX   16
74 #define GENHW_SSH_BINDING_TABLE_ALIGN  32
75 #define GENHW_SSH_BINDING_TABLE_ALIGN_G8  64
76 
77 #define GENHW_SSH_SURFACE_STATES       40
78 #define GENHW_SSH_SURFACE_STATES_MIN   16
79 #define GENHW_SSH_SURFACE_STATES_MAX   256
80 
81 #define GENHW_SSH_SURFACES_PER_BT      64
82 #define GENHW_SSH_SURFACES_PER_BT_MIN  4
83 #define GENHW_SSH_SURFACES_PER_BT_MAX  256
84 
85 #define GENHW_SYNC_SIZE_G75             128
86 
87 #define GENHW_MEDIA_STATES_G75          16
88 
89 #define GENHW_MEDIA_IDS_G75             16
90 
91 #define GENHW_URB_SIZE_MAX_G75          2048
92 
93 #define GENHW_URB_ENTRIES_MAX_G75_GT1   64
94 #define GENHW_URB_ENTRIES_MAX_G75_GT2   64
95 #define GENHW_URB_ENTRIES_MAX_G75_GT3   128
96 
97 #define GENHW_INTERFACE_DESCRIPTOR_ENTRIES_MAX_G75  64
98 
99 #define GENHW_URB_ENTRY_SIZE_MAX_G75   (GENHW_URB_SIZE_MAX_G75 - GENHW_INTERFACE_DESCRIPTOR_ENTRIES_MAX_G75)
100 
101 #define GENHW_CURBE_SIZE_MAX_G75       (GENHW_URB_SIZE_MAX_G75 - GENHW_INTERFACE_DESCRIPTOR_ENTRIES_MAX_G75)
102 
103 #define GENHW_CURBE_SIZE_G75           320
104 #define GENHW_CURBE_SIZE_G8            832
105 
106 #define GENHW_KERNEL_COUNT_G75          32
107 
108 #define GENHW_KERNEL_COUNT_MIN          2
109 
110 #define GENHW_KERNEL_HEAP_G75           2097152
111 
112 #define GENHW_KERNEL_HEAP_MIN           65536
113 #define GENHW_KERNEL_HEAP_MAX           2097152
114 
115 #define GENHW_KERNEL_BLOCK_SIZE_G75     65536
116 
117 #define GENHW_KERNEL_BLOCK_MIN          1024
118 #define GENHW_KERNEL_BLOCK_MAX          65536
119 
120 #define GENHW_SUBSLICES_MAX_G75_GT1         1
121 #define GENHW_SUBSLICES_MAX_G75_GT2         2
122 #define GENHW_SUBSLICES_MAX_G75_GT3         4
123 #define GENHW_SUBSLICES_MAX_G8_GT1          1
124 #define GENHW_SUBSLICES_MAX_G8_GT2          2
125 #define GENHW_SUBSLICES_MAX_G8_GT3          4
126 #define GENHW_SUBSLICES_MAX_G8_LCIA         2
127 
128 #define GENHW_EU_INDEX_MAX_G75              13
129 #define GENHW_EU_INDEX_MAX_G8               12
130 
131 #define GENHW_MEDIA_THREADS_PER_EU_MAX_G75  7
132 #define GENHW_MEDIA_THREADS_PER_EU_MAX_G8   7
133 
134 #define GENHW_SIZE_REGISTERS_PER_THREAD_G75 0x1140
135 #define GENHW_SIZE_REGISTERS_PER_THREAD_G8  0x1800
136 
137 #define GENHW_USE_MEDIA_THREADS_MAX         0
138 #define GENHW_MEDIA_THREADS_MAX_G75_GT1     70
139 #define GENHW_MEDIA_THREADS_MAX_G75_GT2     140
140 #define GENHW_MEDIA_THREADS_MAX_G75_GT3     280
141 #define GENHW_MEDIA_THREADS_MAX_G8_GT1      84
142 #define GENHW_MEDIA_THREADS_MAX_G8_GT2      168
143 #define GENHW_MEDIA_THREADS_MAX_G8_GT3      336
144 #define GENHW_MEDIA_THREADS_MAX_G8_LCIA     112
145 
146 #define GENHW_MEDIAL_SUBSLICE_SCRATCH_DISTANCE_G75 128
147 
148 #define GENHW_MAX_SIP_SIZE              0x4000
149 
150 #define GENHW_KERNEL_BLOCK_ALIGN        64
151 #define GENHW_URB_BLOCK_ALIGN           64
152 #define GENHW_SYNC_BLOCK_ALIGN          128
153 #define GENHW_CURBE_BLOCK_ALIGN_G7      32
154 #define GENHW_CURBE_BLOCK_ALIGN_G8      64
155 
156 #define GENHW_INSTRUCTION_CACHE_G75     1500
157 
158 #define GENHW_TIMEOUT_MS_DEFAULT        100
159 #define GENHW_EVENT_TIMEOUT_MS          5
160 
161 #define GENHW_MAX_DEPENDENCY_COUNT  8
162 
163 typedef enum _GENHW_SURFACE_STATE_TYPE {
164 	GENHW_SURFACE_TYPE_INVALID = 0,
165 	GENHW_SURFACE_TYPE_G5,
166 	GENHW_SURFACE_TYPE_G6,
167 	GENHW_SURFACE_TYPE_G7,
168 	GENHW_SURFACE_TYPE_G8,
169 	GENHW_SURFACE_TYPE_G9,
170 } GENHW_SURFACE_STATE_TYPE, *PGENHW_SURFACE_STATE_TYPE;
171 
172 typedef enum _GENHW_MEDIA_WALKER_MODE {
173 	GENHW_MEDIA_WALKER_MODE_NOT_SET = -1,
174 	GENHW_MEDIA_WALKER_DISABLED = 0,
175 	GENHW_MEDIA_WALKER_REPEL_MODE,
176 	GENHW_MEDIA_WALKER_DUAL_MODE,
177 	GENHW_MEDIA_WALKER_QUAD_MODE
178 } GENHW_MEDIA_WALKER_MODE;
179 
180 typedef enum _GENHW_PLANE {
181 	GENHW_GENERIC_PLANE = 0,
182 	GENHW_Y_PLANE,
183 	GENHW_U_PLANE,
184 	GENHW_V_PLANE
185 } GENHW_PLANE;
186 
187 typedef enum _GENHW_PLANE_DEFINITION {
188 	GENHW_PLANES_PL3 = 0,
189 	GENHW_PLANES_NV12,
190 	GENHW_PLANES_YUY2,
191 	GENHW_PLANES_UYVY,
192 	GENHW_PLANES_YVYU,
193 	GENHW_PLANES_VYUY,
194 	GENHW_PLANES_ARGB,
195 	GENHW_PLANES_XRGB,
196 	GENHW_PLANES_ABGR,
197 	GENHW_PLANES_XBGR,
198 	GENHW_PLANES_RGB16,
199 	GENHW_PLANES_R16U,
200 	GENHW_PLANES_R16S,
201 	GENHW_PLANES_R32U,
202 	GENHW_PLANES_R32S,
203 	GENHW_PLANES_R32F,
204 	GENHW_PLANES_V8U8,
205 	GENHW_PLANES_R8G8_UNORM,
206 	GENHW_PLANES_411P,
207 	GENHW_PLANES_411R,
208 	GENHW_PLANES_422H,
209 	GENHW_PLANES_422V,
210 	GENHW_PLANES_444P,
211 	GENHW_PLANES_RGBP,
212 	GENHW_PLANES_BGRP,
213 
214 	GENHW_PLANES_AI44_PALLETE_0,
215 	GENHW_PLANES_IA44_PALLETE_0,
216 	GENHW_PLANES_P8_PALLETE_0,
217 	GENHW_PLANES_A8P8_PALLETE_0,
218 	GENHW_PLANES_AI44_PALLETE_1,
219 	GENHW_PLANES_IA44_PALLETE_1,
220 	GENHW_PLANES_P8_PALLETE_1,
221 	GENHW_PLANES_A8P8_PALLETE_1,
222 
223 	GENHW_PLANES_AYUV,
224 	GENHW_PLANES_STMM,
225 	GENHW_PLANES_L8,
226 
227 	GENHW_PLANES_A8,
228 	GENHW_PLANES_R8,
229 	GENHW_PLANES_NV12_2PLANES,
230 	GENHW_PLANES_R16_UNORM,
231 	GENHW_PLANES_Y8,
232 	GENHW_PLANES_Y1,
233 	GENHW_PLANES_Y16U,
234 	GENHW_PLANES_Y16S,
235 	GENHW_PLANES_A16B16G16R16,
236 	GENHW_PLANES_R10G10B10A2,
237 	GENHW_PLANES_L16,
238 	GENHW_PLANES_NV21,
239 	GENHW_PLANES_YV12,
240 	GENHW_PLANES_P016,
241 	GENHW_PLANES_P010,
242 	GENHW_PLANES_DEFINITION_COUNT
243 } GENHW_PLANE_DEFINITION, *PGENHW_PLANE_DEFINITION;
244 
245 #define GENHW_MEMORY_OBJECT_CONTROL     DWORD
246 
247 typedef struct _GENHW_L3_CACHE_CONFIG {
248 	DWORD   dwL3SQCReg1;
249 	DWORD   dwL3CntlReg;
250 	DWORD   dwL3CntlReg2;
251 	DWORD   dwL3CntlReg3;
252 	DWORD   dwL3LRA1Reg;
253 	DWORD   dwL3SQCReg4;
254 } GENHW_L3_CACHE_CONFIG, *PGENHW_L3_CACHE_CONFIG;
255 
256 typedef enum _GENHW_INDIRECT_PATCH_CMD {
257 	CMD_INDIRECT_INVALID,
258 	CMD_INDIRECT_PIPE_CONTROL,
259 	CMD_INDIRECT_MI_STORE_DATA_IMM,
260 	CMD_INDIRECT_MAX
261 } GENHW_INDIRECT_PATCH_COMMAND;
262 
263 typedef struct _GENHW_PLANE_SETTING {
264 	BYTE PlaneID;
265 	BYTE ScaleWidth;
266 	BYTE ScaleHeight;
267 	BYTE AlignWidth;
268 	BYTE AlignHeight;
269 	BYTE PixelsPerDword;
270 	BOOL bAdvanced;
271 	DWORD dwFormat;
272 } GENHW_PLANE_SETTING, *PGENHW_PLANE_SETTING;
273 
274 typedef struct _GENHW_SURFACE_PLANES {
275 	int NumPlanes;
276 	GENHW_PLANE_SETTING Plane[GENHW_MAX_SURFACE_PLANES];
277 } GENHW_SURFACE_PLANES, *PGENHW_SURFACE_PLANES;
278 
279 typedef struct _GENHW_KERNEL_PARAM {
280 	INT GRF_Count;
281 	INT BT_Count;
282 	INT Thread_Count;
283 	INT GRF_Start_Register;
284 	INT CURBE_Length;
285 	INT block_width;
286 	INT block_height;
287 	INT blocks_x;
288 	INT blocks_y;
289 } GENHW_KERNEL_PARAM, *PGENHW_KERNEL_PARAM;
290 
291 typedef struct _GENHW_KERNEL_ENTRY {
292 	LPCSTR pszName;
293 	PVOID pExtra;
294 	PBYTE pBinary;
295 	INT iSize;
296 } GENHW_KERNEL_ENTRY, *PGENHW_KERNEL_ENTRY;
297 
298 typedef struct _GENHW_KERNEL_CACHE {
299 	INT iNumKernels;
300 	GENHW_KERNEL_ENTRY pKernelEntry;
301 	PBYTE pKernelBase;
302 } GENHW_KERNEL_CACHE, *PGENHW_KERNEL_CACHE;
303 
304 typedef struct _GENHW_KRN_ALLOCATION {
305 	INT iKID;
306 	INT iKUID;
307 	INT iKCID;
308 	DWORD dwSync;
309 	DWORD dwOffset;
310 	INT iSize;
311 	DWORD dwFlags:4;
312 	DWORD dwCount:28;
313 	GENHW_KERNEL_PARAM Params;
314 	Kdll_CacheEntry *pKernel;
315 } GENHW_KRN_ALLOCATION, *PGENHW_KRN_ALLOCATION;
316 
317 typedef struct _GENHW_MEDIA_STATE {
318 	DWORD dwOffset;
319 	PINT piAllocation;
320 
321 	DWORD dwSyncTag;
322 	DWORD dwSyncCount;
323 	INT iCurbeOffset;
324 	DWORD bBusy:1;
325 	 DWORD:31;
326 } GENHW_MEDIA_STATE, *PGENHW_MEDIA_STATE;
327 
328 typedef struct _GENHW_BATCH_BUFFER *PGENHW_BATCH_BUFFER;
329 typedef struct _GENHW_BATCH_BUFFER_PARAMS *PGENHW_BATCH_BUFFER_PARAMS;
330 
331 typedef struct _GENHW_BATCH_BUFFER {
332 	GENOS_RESOURCE OsResource;
333 	INT iSize;
334 	INT iCurrent;
335 	BOOL bLocked;
336 	PBYTE pData;
337 
338 	BOOL bBusy;
339 	DWORD dwSyncTag;
340 	PGENHW_BATCH_BUFFER pNext;
341 	PGENHW_BATCH_BUFFER pPrev;
342 
343 	PGENHW_BATCH_BUFFER_PARAMS pBBRenderData;
344 } GENHW_BATCH_BUFFER;
345 
346 typedef struct _GENHW_VFE_STATE_PARAMS {
347 	DWORD dwDebugCounterControl;
348 	DWORD dwMaximumNumberofThreads;
349 	DWORD dwCURBEAllocationSize;
350 	DWORD dwURBEntryAllocationSize;
351 } GENHW_VFE_STATE_PARAMS;
352 
353 typedef struct _GENHW_HW_CAPS {
354 	DWORD dwMaxBTIndex;
355 	DWORD dwMaxThreads;
356 	DWORD dwMaxMediaPayloadSize;
357 	DWORD dwMaxURBSize;
358 	DWORD dwMaxURBEntries;
359 	DWORD dwMaxURBEntryAllocationSize;
360 	DWORD dwMaxCURBEAllocationSize;
361 	DWORD dwMaxInterfaceDescriptorEntries;
362 	DWORD dwMaxSubslice;
363 	DWORD dwMaxEUIndex;
364 	DWORD dwNumThreadsPerEU;
365 	DWORD dwSizeRegistersPerThread;
366 } GENHW_HW_CAPS, *PGENHW_HW_CAPS;
367 typedef CONST struct _GENHW_HW_CAPS *PCGENHW_HW_CAPS;
368 
369 typedef struct _GENHW_GSH_SETTINGS {
370 	INT iSyncSize;
371 	INT iMediaStateHeaps;
372 	INT iMediaIDs;
373 	INT iCurbeSize;
374 	INT iKernelCount;
375 	INT iKernelHeapSize;
376 	INT iKernelBlockSize;
377 
378 	INT iPerThreadScratchSize;
379 	INT iSipSize;
380 } GENHW_GSH_SETTINGS, *PGENHW_GSH_SETTINGS;
381 
382 typedef struct _GENHW_SSH_SETTINGS {
383 	INT iSurfaceStateHeaps;
384 	INT iBindingTables;
385 	INT iSurfaceStates;
386 	INT iSurfacesPerBT;
387 	INT iBTAlignment;
388 } GENHW_SSH_SETTINGS, *PGENHW_SSH_SETTINGS;
389 
390 typedef struct _GENHW_GSH {
391 	GENOS_RESOURCE OsResource;
392 	DWORD dwGSHSize;
393 	BOOL bGSHLocked;
394 	PBYTE pGSH;
395 
396 	DWORD dwOffsetSync;
397 	DWORD dwSizeSync;
398 
399 	volatile PDWORD pSync;
400 	DWORD dwNextTag;
401 	DWORD dwSyncTag;
402 
403 	INT iCurMediaState;
404 	INT iNextMediaState;
405 	PGENHW_MEDIA_STATE pCurMediaState;
406 
407 	DWORD dwOffsetMediaID;
408 	DWORD dwSizeMediaID;
409 
410 	DWORD dwOffsetCurbe;
411 	DWORD dwSizeCurbe;
412 
413 	DWORD dwKernelBase;
414 	INT iKernelSize;
415 	INT iKernelUsed;
416 	PBYTE pKernelLoadMap;
417 	DWORD dwAccessCounter;
418 
419 	DWORD dwScratchSpaceSize;
420 	DWORD dwScratchSpaceBase;
421 
422 	DWORD dwSipBase;
423 
424 	PGENHW_KRN_ALLOCATION pKernelAllocation;
425 	PGENHW_MEDIA_STATE pMediaStates;
426 } GENHW_GSH, *PGENHW_GSH;
427 
428 typedef struct _GENHW_VFE_SCOREBOARD_DELTA {
429 	BYTE x:4;
430 	BYTE y:4;
431 } GENHW_VFE_SCOREBOARD_DELTA, *PGENHW_VFE_SCOREBOARD_DELTA;
432 
433 typedef struct _GENHW_VFE_SCOREBOARD {
434 	struct {
435 		DWORD ScoreboardMask:8;
436 		 DWORD:22;
437 		DWORD ScoreboardType:1;
438 		DWORD ScoreboardEnable:1;
439 	};
440 
441 	union {
442 		GENHW_VFE_SCOREBOARD_DELTA
443 		    ScoreboardDelta[GENHW_MAX_DEPENDENCY_COUNT];
444 		struct {
445 			DWORD Value[2];
446 		};
447 	};
448 
449 } GENHW_VFE_SCOREBOARD, *PGENHW_VFE_SCOREBOARD;
450 
451 typedef struct _GENHW_WALKER_XY {
452 	union {
453 		struct {
454 			DWORD x:16;
455 			DWORD y:16;
456 		};
457 		DWORD value;
458 	};
459 } GENHW_WALKER_XY, *PGENHW_WALKER_XY;
460 
461 typedef struct _GENHW_WALKER_PARAMS {
462 	DWORD InterfaceDescriptorOffset:5;
463 	DWORD CmWalkerEnable:1;
464 	DWORD ColorCountMinusOne:4;
465 	DWORD ScoreboardMask:8;
466 	DWORD MidLoopUnitX:2;
467 	DWORD MidLoopUnitY:2;
468 	DWORD MiddleLoopExtraSteps:5;
469 	 DWORD:5;
470 	DWORD InlineDataLength;
471 	PBYTE pInlineData;
472 	GENHW_WALKER_XY LoopExecCount;
473 	GENHW_WALKER_XY BlockResolution;
474 	GENHW_WALKER_XY LocalStart;
475 	GENHW_WALKER_XY LocalEnd;
476 	GENHW_WALKER_XY LocalOutLoopStride;
477 	GENHW_WALKER_XY LocalInnerLoopUnit;
478 	GENHW_WALKER_XY GlobalResolution;
479 	GENHW_WALKER_XY GlobalStart;
480 	GENHW_WALKER_XY GlobalOutlerLoopStride;
481 	GENHW_WALKER_XY GlobalInnerLoopUnit;
482 } GENHW_WALKER_PARAMS, *PGENHW_WALKER_PARAMS;
483 
484 typedef struct _GENHW_GPGPU_WALKER_PARAMS {
485 	DWORD InterfaceDescriptorOffset:5;
486 	DWORD GpGpuEnable:1;
487 	 DWORD:26;
488 	DWORD ThreadWidth;
489 	DWORD ThreadHeight;
490 	DWORD GroupWidth;
491 	DWORD GroupHeight;
492 	DWORD SLMSize;
493 } GENHW_GPGPU_WALKER_PARAMS, *PGENHW_GPGPU_WALKER_PARAMS;
494 
495 typedef struct _GENHW_INTERFACE_DESCRIPTOR_PARAMS {
496 	INT iMediaID;
497 	INT iBindingTableID;
498 	INT iCurbeOffset;
499 	INT iCurbeLength;
500 	INT iCrsThrdConstDataLn;
501 } GENHW_INTERFACE_DESCRIPTOR_PARAMS, *PGENHW_INTERFACE_DESCRIPTOR_PARAMS;
502 
503 typedef struct _GENHW_HW_MEDIAOBJECT_PARAM {
504 	DWORD dwIDOffset;
505 	DWORD dwMediaObjectSize;
506 } GENHW_HW_MEDIAOBJECT_PARAM, *PGENHW_HW_MEDIAOBJECT_PARAM;
507 
508 typedef struct _GENHW_INDIRECT_PATCH_PARAM {
509 	GENHW_INDIRECT_PATCH_COMMAND Command;
510 	PGENOS_RESOURCE pSrcOsResource;
511 	DWORD dwSrcOffset;
512 	PGENOS_RESOURCE pTgtOsResource;
513 	DWORD dwTgtOffset;
514 } GENHW_INDIRECT_PATCH_PARAM, *PGENHW_INDIRECT_PATCH_PARAM;
515 
516 typedef struct _GENHW_PIPECONTROL_PARAM {
517 	PGENOS_RESOURCE pOsResource;
518 	DWORD dwOffset;
519 	GFX3DCONTROL_OPERATION Operation;
520 	DWORD dwImmData;
521 	DWORD dwInvalidateStateCache:1;
522 	DWORD dwInvaliateConstantCache:1;
523 	DWORD dwInvalidateVFECache:1;
524 	DWORD dwInvalidateInstructionCache:1;
525 	DWORD dwFlushRenderTargetCache:1;
526 	DWORD dwCSStall:1;
527 	DWORD dwTlbInvalidate:1;
528 } GENHW_PIPECONTROL_PARAM, *PGENHW_PIPECONTROL_PARAM;
529 
530 typedef struct _GENHW_STORE_DATA_IMM_PARAM {
531 	PGENOS_RESOURCE pOsResource;
532 	DWORD dwOffset;
533 	DWORD dwValue;
534 } GENHW_STORE_DATA_IMM_PARAM, *PGENHW_STORE_DATA_IMM_PARAM;
535 
536 typedef struct _GENHW_LOAD_REGISTER_IMM_PARAM {
537 	PGENOS_RESOURCE pOsResource;
538 	DWORD dwRegisterAddress;
539 	DWORD dwData;
540 } GENHW_LOAD_REGISTER_IMM_PARAM, *PGENHW_LOAD_REGISTER_IMM_PARAM;
541 
542 typedef struct _GENHW_SCOREBOARD_PARAMS {
543 	BYTE numMask;
544 	BYTE ScoreboardType;
545 	GENHW_VFE_SCOREBOARD_DELTA ScoreboardDelta[GENHW_MAX_DEPENDENCY_COUNT];
546 } GENHW_SCOREBOARD_PARAMS, *PGENHW_SCOREBOARD_PARAMS;
547 
548 typedef struct _GENHW_SURFACE_STATE_PARAMS {
549 	GENHW_SURFACE_STATE_TYPE Type:5;
550 	DWORD bRenderTarget:1;
551 	DWORD bVertStride:1;
552 	DWORD bVertStrideOffs:1;
553 	DWORD bWidthInDword_Y:1;
554 	DWORD bWidthInDword_UV:1;
555 	DWORD bAVS:1;
556 	DWORD bWidth16Align:1;
557 	DWORD b2PlaneNV12NeededByKernel:1;
558 	DWORD bForceNV12:1;
559 	DWORD bUncoded:1;
560 	DWORD b32MWColorFillKernWA:1;
561 	DWORD bVASurface:1;
562 	DWORD AddressControl:2;
563 	DWORD bWAUseSrcHeight:1;
564 	DWORD bWAUseSrcWidth:1;
565 	 DWORD:8;
566 	GENHW_MEMORY_OBJECT_CONTROL MemObjCtl;
567 } GENHW_SURFACE_STATE_PARAMS, *PGENHW_SURFACE_STATE_PARAMS;
568 
569 typedef union _GENHW_SURFACE_STATE {
570 	PACKET_SURFACE_STATE_G75 PacketSurfaceState_g75;
571 	PACKET_SURFACE_STATE_G8 PacketSurfaceState_g8;
572 	PACKET_SURFACE_STATE_G9 PacketSurfaceState_g9;
573 } GENHW_SURFACE_STATE, *PGENHW_SURFACE_STATE;
574 
575 typedef struct _GENHW_SURFACE_STATE_ENTRY {
576 	GENHW_SURFACE_STATE_TYPE Type;
577 	PGENHW_SURFACE pGenHwSurface;
578 	PGENHW_SURFACE_STATE pSurfaceState;
579 	INT iSurfStateID;
580 	DWORD dwSurfStateOffset;
581 	DWORD dwFormat;
582 	DWORD dwWidth;
583 	DWORD dwHeight;
584 	DWORD dwPitch;
585 	DWORD YUVPlane:2;
586 	DWORD bAVS:1;
587 	DWORD bRenderTarget:1;
588 	DWORD bVertStride:1;
589 	DWORD bVertStrideOffs:1;
590 	DWORD bWidthInDword:1;
591 	DWORD bTiledSurface:1;
592 	DWORD bTileWalk:1;
593 	DWORD bHalfPitchChroma:1;
594 	DWORD bInterleaveChroma:1;
595 	DWORD DirectionV:3;
596 	DWORD DirectionU:1;
597 	DWORD AddressControl:2;
598 	 DWORD:15;
599 	WORD wUXOffset;
600 	WORD wUYOffset;
601 	WORD wVXOffset;
602 	WORD wVYOffset;
603 } GENHW_SURFACE_STATE_ENTRY, *PGENHW_SURFACE_STATE_ENTRY;
604 
605 typedef struct _GENHW_SSH {
606 	GENOS_RESOURCE OsResource;
607 	PBYTE pSshBuffer;
608 	DWORD dwSshSize;
609 	DWORD dwSshIntanceSize;
610 	BOOL bLocked;
611 
612 	INT iBindingTableSize;
613 	INT iBindingTableOffset;
614 	INT iSurfaceStateOffset;
615 
616 	PGENHW_SURFACE_STATE_ENTRY pSurfaceEntry;
617 
618 	INT iCurSshBufferIndex;
619 	INT iCurrentBindingTable;
620 	INT iCurrentSurfaceState;
621 } GENHW_SSH, *PGENHW_SSH;
622 
623 typedef CONST struct _GENHW_PLANE_SETTING CGENHW_PLANE_SETTING,
624     *PCGENHW_PLANE_SETTING;
625 
626 typedef CONST struct _GENHW_SURFACE_PLANES CGENHW_SURFACE_PLANES,
627     *PCGENHW_SURFACE_PLANES;
628 
629 typedef CONST struct _GENHW_GSH_SETTINGS CGENHW_GSH_SETTINGS,
630     *PCGENHW_GSH_SETTINGS;
631 
632 typedef CONST struct _GENHW_SSH_SETTINGS CGENHW_SSH_SETTINGS,
633     *PCGENHW_SSH_SETTINGS;
634 
635 typedef CONST struct _GENHW_KERNEL_PARAM CGENHW_KERNEL_PARAM,
636     *PCGENHW_KERNEL_PARAM;
637 
638 typedef struct _MEDIA_OBJECT_KA2_CMD {
639 	MEDIA_OBJECT_FC_CMD_G6 MediaObjectFC;
640 } MEDIA_OBJECT_KA2_CMD, *PMEDIA_OBJECT_KA2_CMD;
641 
642 typedef struct _GENHW_HW_COMMANDS {
643 	PLATFORM Platform;
644 
645 	DWORD dwMediaObjectHeaderCmdSize;
646 
647 	CONST SURFACE_STATE_G7 *pSurfaceState_g75;
648 	CONST SURFACE_STATE_G8 *pSurfaceState_g8;
649 	CONST SURFACE_STATE_G9 *pSurfaceState_g9;
650 
651 	CONST BINDING_TABLE_STATE_G5 *pBindingTableState_g75;
652 	CONST BINDING_TABLE_STATE_G8 *pBindingTableState_g8;
653 
654 	CONST MI_BATCH_BUFFER_END_CMD_G5 *pBatchBufferEnd;
655 
656 	CONST PIPELINE_SELECT_CMD_G5 *pPipelineSelectMedia;
657 
658 	CONST SURFACE_STATE_TOKEN_G75 *pSurfaceStateToken_g75;
659 
660 	CONST MEDIA_VFE_STATE_CMD_G6 *pVideoFrontEnd_g75;
661 	CONST MEDIA_CURBE_LOAD_CMD_G6 *pMediaCurbeLoad_g75;
662 	CONST MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD_G6 *pMediaIDLoad_g75;
663 	CONST MEDIA_OBJECT_WALKER_CMD_G6 *pMediaWalker_g75;
664 	CONST GPGPU_WALKER_CMD_G75 *pGpGpuWalker_g75;
665 	CONST INTERFACE_DESCRIPTOR_DATA_G6 *pInterfaceDescriptor_g75;
666 	CONST MI_LOAD_REGISTER_IMM_CMD_G6 *pLoadRegImm_g75;
667 
668 	CONST PIPE_CONTROL_CMD_G7 *pPipeControl_g75;
669 
670 	CONST MEDIA_STATE_FLUSH_CMD_G75 *pMediaStateFlush_g75;
671 
672 	CONST GENHW_PIPECONTROL_PARAM *pcPipeControlParam;
673 	CONST GENHW_STORE_DATA_IMM_PARAM *pcStoreDataImmParam;
674 	CONST GENHW_INDIRECT_PATCH_PARAM *pcPatchParam;
675 
676 	CONST STATE_BASE_ADDRESS_CMD_G75 *pStateBaseAddress_g75;
677 	CONST MI_BATCH_BUFFER_START_CMD_G75 *pBatchBufferStart_g75;
678 	CONST MI_ARB_CHECK_CMD_G75 *pArbCheck_g75;
679 
680 	CONST PIPE_CONTROL_CMD_G8 *pPipeControl_g8;
681 	CONST INTERFACE_DESCRIPTOR_DATA_G8 *pInterfaceDescriptor_g8;
682 	CONST STATE_BASE_ADDRESS_CMD_G8 *pStateBaseAddress_g8;
683 	CONST MI_BATCH_BUFFER_START_CMD_G8 *pBatchBufferStart_g8;
684 	CONST MEDIA_VFE_STATE_CMD_G8 *pVideoFrontEnd_g8;
685 	CONST GPGPU_WALKER_CMD_G8 *pGpGpuWalker_g8;
686 
687 	CONST MEDIA_VFE_STATE_CMD_G9 *pVideoFrontEnd_g9;
688 	CONST MEDIA_OBJECT_WALKER_CMD_G9 *pMediaWalker_g9;
689 	CONST PIPELINE_SELECT_CMD_G9 *pPipelineSelectMedia_g9;
690 
691 	MEDIA_OBJECT_HEADER_G6 MediaObjectIStabGMC_g75;
692 
693 } GENHW_HW_COMMANDS, *PGENHW_HW_COMMANDS;
694 
695 typedef struct _GENHW_HW_INTERFACE {
696 	PGENOS_INTERFACE pOsInterface;
697 	PGENHW_HW_COMMANDS pHwCommands;
698 	PGENHW_GSH pGeneralStateHeap;
699 	PGENHW_SSH pSurfaceStateHeap;
700 
701 	PGENHW_BATCH_BUFFER pBatchBufferList;
702 
703 	PLATFORM Platform;
704 
705 	GENHW_VFE_SCOREBOARD VfeScoreboard;
706 	PCGENHW_SURFACE_PLANES pPlaneDefinitions;
707 
708 	PCGENHW_HW_CAPS pHwCaps;
709 	GENHW_GSH_SETTINGS GshSettings;
710 	GENHW_SSH_SETTINGS SshSettings;
711 
712 	GENHW_VFE_STATE_PARAMS VfeStateParams;
713 
714 	GENHW_SURFACE_STATE_TYPE SurfaceTypeDefault;
715 
716 	BOOL bEnableYV12SinglePass;
717 	BOOL bMediaReset;
718 	BOOL bUsesPatchList;
719 	BOOL bRequestSingleSlice;
720 	BOOL bSysRoutine;
721 
722 	GENHW_MEDIA_WALKER_MODE MediaWalkerMode;
723 	DWORD dwIndirectHeapSize;
724 	DWORD dwTimeoutMs;
725 
726 	INT iSizeBindingTableState;
727 	INT iSizeInstructionCache;
728 
729 	INT iSizeInterfaceDescriptor;
730 
731 	INT iMediaStatesInUse;
732 	INT iBuffersInUse;
733 
734 	 GENOS_STATUS(*pfnInitialize) (PGENHW_HW_INTERFACE pHwInterface,
735 				       PCGENHW_SETTINGS pSettings);
736 
737 	 VOID(*pfnDestroy) (PGENHW_HW_INTERFACE pHwInterface);
738 
739 	 GENOS_STATUS(*pfnResetHwStates) (PGENHW_HW_INTERFACE pHwInterface);
740 
741 	 PGENOS_INTERFACE(*pfnGetOsInterface) (PGENHW_HW_INTERFACE
742 					       pHwInterface);
743 
744 	 GENOS_STATUS(*pfnAllocateCommands) (PGENHW_HW_INTERFACE pHwInterface);
745 
746 	 VOID(*pfnFreeCommands) (PGENHW_HW_INTERFACE pHwInterface);
747 
748 	 VOID(*pfnInitCommandsCommon) (PGENHW_HW_INTERFACE pHwInterface);
749 
750 	 VOID(*pfnInitCommands) (PGENHW_HW_INTERFACE pHwInterface);
751 
752 	 GENOS_STATUS(*pfnAllocateSSH) (PGENHW_HW_INTERFACE pHwInterface,
753 					PCGENHW_SSH_SETTINGS pSshSettings);
754 
755 	 VOID(*pfnFreeSSH) (PGENHW_HW_INTERFACE pHwInterface);
756 
757 	 GENOS_STATUS(*pfnAllocateSshBuffer) (PGENHW_HW_INTERFACE pHwInterface,
758 					      PGENHW_SSH pSSH);
759 
760 	 VOID(*pfnFreeSshBuffer) (PGENHW_HW_INTERFACE pHwInterface,
761 				  PGENHW_SSH pSSH);
762 
763 	 GENOS_STATUS(*pfnAssignSshInstance) (PGENHW_HW_INTERFACE pHwInterface);
764 
765 	 GENOS_STATUS(*pfnGetSurfaceStateEntries) (PGENHW_HW_INTERFACE
766 						   pHwInterface,
767 						   PGENHW_SURFACE pSurface,
768 						   PGENHW_SURFACE_STATE_PARAMS
769 						   pParams, PINT piNumEntries,
770 						   PGENHW_SURFACE_STATE_ENTRY *
771 						   ppSurfaceEntries);
772 
773 	 GENOS_STATUS(*pfnSetupSurfaceState) (PGENHW_HW_INTERFACE pHwInterface,
774 					      PGENHW_SURFACE pSurface,
775 					      PGENHW_SURFACE_STATE_PARAMS
776 					      pParams, PINT piNumEntries,
777 					      PGENHW_SURFACE_STATE_ENTRY *
778 					      ppSurfaceEntries);
779 
780 	 GENOS_STATUS(*pfnAssignSurfaceState) (PGENHW_HW_INTERFACE pHwInterface,
781 					       GENHW_SURFACE_STATE_TYPE Type,
782 					       PGENHW_SURFACE_STATE_ENTRY *
783 					       ppSurfaceEntry);
784 
785 	 VOID(*pfnGetAlignUnit) (PWORD pwWidthAlignUnit,
786 				 PWORD pwHeightAlignUnit,
787 				 PGENHW_SURFACE pSurface);
788 
789 	 VOID(*pfnAdjustBoundary) (PGENHW_HW_INTERFACE pHwInterface,
790 				   PGENHW_SURFACE pSurface,
791 				   PDWORD pdwSurfaceWidth,
792 				   PDWORD pdwSurfaceHeight);
793 
794 	 GENOS_STATUS(*pfnAssignBindingTable) (PGENHW_HW_INTERFACE pHwInterface,
795 					       PINT piBindingTable);
796 
797 	 GENOS_STATUS(*pfnBindSurfaceState) (PGENHW_HW_INTERFACE pHwInterface,
798 					     INT iBindingTableIndex,
799 					     INT iBindingTableEntry,
800 					     PGENHW_SURFACE_STATE_ENTRY
801 					     pSurfaceEntry);
802 
803 	 DWORD(*pfnGetSurfaceMemoryObjectControl) (PGENHW_HW_INTERFACE
804 						   pHwInterface,
805 						   PGENHW_SURFACE_STATE_PARAMS
806 						   pParams);
807 
808 	 GENOS_STATUS(*pfnSetupSurfaceStateOs) (PGENHW_HW_INTERFACE
809 						pHwInterface,
810 						PGENHW_SURFACE pSurface,
811 						PGENHW_SURFACE_STATE_PARAMS
812 						pParams,
813 						PGENHW_SURFACE_STATE_ENTRY
814 						pSurfaceStateEntry);
815 
816 	 GENOS_STATUS(*pfnAllocateGSH) (PGENHW_HW_INTERFACE pHwInterface,
817 					PCGENHW_GSH_SETTINGS pGshSettings);
818 
819 	 GENOS_STATUS(*pfnFreeGSH) (PGENHW_HW_INTERFACE pHwInterface);
820 
821 	 GENOS_STATUS(*pfnLockGSH) (PGENHW_HW_INTERFACE pHwInterface);
822 
823 	 GENOS_STATUS(*pfnUnlockGSH) (PGENHW_HW_INTERFACE pHwInterface);
824 
825 	 GENOS_STATUS(*pfnResetGSH) (PGENHW_HW_INTERFACE pHwInterface);
826 
827 	 GENOS_STATUS(*pfnRefreshSync) (PGENHW_HW_INTERFACE pHwInterface);
828 
829 	 GENOS_STATUS(*pfnAllocateBB) (PGENHW_HW_INTERFACE pHwInterface,
830 				       PGENHW_BATCH_BUFFER pBatchBuffer,
831 				       INT iSize);
832 
833 	 GENOS_STATUS(*pfnFreeBB) (PGENHW_HW_INTERFACE pHwInterface,
834 				   PGENHW_BATCH_BUFFER pBatchBuffer);
835 
836 	 GENOS_STATUS(*pfnLockBB) (PGENHW_HW_INTERFACE pHwInterface,
837 				   PGENHW_BATCH_BUFFER pBatchBuffer);
838 
839 	 GENOS_STATUS(*pfnUnlockBB) (PGENHW_HW_INTERFACE pHwInterface,
840 				     PGENHW_BATCH_BUFFER pBatchBuffer);
841 
842 	 PGENHW_MEDIA_STATE(*pfnAssignMediaState) (PGENHW_HW_INTERFACE
843 						   pHwInterface);
844 
845 	 INT(*pfnLoadCurbeData) (PGENHW_HW_INTERFACE pHwInterface,
846 				 PGENHW_MEDIA_STATE pMediaState,
847 				 PVOID pData, INT iSize);
848 
849 	 VOID(*pfnInitInterfaceDescriptor) (PGENHW_HW_INTERFACE pHwInterface,
850 					    PBYTE pBase,
851 					    DWORD dwBase, DWORD dwOffsetID);
852 
853 	 VOID(*pfnSetupInterfaceDescriptor) (PGENHW_HW_INTERFACE pHwInterface,
854 					     PGENHW_MEDIA_STATE pMediaState,
855 					     PGENHW_KRN_ALLOCATION
856 					     pKernelAllocation,
857 					     PGENHW_INTERFACE_DESCRIPTOR_PARAMS
858 					     pInterfaceDescriptorParams,
859 					     PGENHW_GPGPU_WALKER_PARAMS
860 					     pGpGpuWalkerParams);
861 
862 	 VOID(*pfnSetVfeStateParams) (PGENHW_HW_INTERFACE pHwInterface,
863 				      DWORD dwDebugCounterControl,
864 				      DWORD dwMaximumNumberofThreads,
865 				      DWORD dwCURBEAllocationSize,
866 				      DWORD dwURBEntryAllocationSize,
867 				      PGENHW_SCOREBOARD_PARAMS
868 				      pScoreboardParams);
869 
870 	 BOOL(*pfnGetMediaWalkerStatus) (PGENHW_HW_INTERFACE pHwInterface);
871 
872 	 UINT(*pfnGetMediaWalkerBlockSize) (PGENHW_HW_INTERFACE pHwInterface);
873 
874 	 GENOS_STATUS(*pfnSendMediaStateFlush) (PGENHW_HW_INTERFACE
875 						pHwInterface,
876 						PGENOS_COMMAND_BUFFER
877 						pCmdBuffer);
878 
879 	 GENOS_STATUS(*pfnSendCommandBufferHeader) (PGENHW_HW_INTERFACE
880 						    pHwInterface,
881 						    PGENOS_COMMAND_BUFFER
882 						    pCmdBuffer);
883 
884 	 GENOS_STATUS(*pfnSendSurfaces) (PGENHW_HW_INTERFACE pHwInterface,
885 					 PGENOS_COMMAND_BUFFER pCmdBuffer);
886 
887 	 GENOS_STATUS(*pfnSendSyncTag) (PGENHW_HW_INTERFACE pHwInterface,
888 					PGENOS_COMMAND_BUFFER pCmdBuffer);
889 
890 	 GENOS_STATUS(*pfnSendStateBaseAddr) (PGENHW_HW_INTERFACE pHwInterface,
891 					      PGENOS_COMMAND_BUFFER pCmdBuffer);
892 
893 	 GENOS_STATUS(*pfnSendPipelineSelectCmd) (PGENHW_HW_INTERFACE
894 						  pHwInterface,
895 						  PGENOS_COMMAND_BUFFER
896 						  pCmdBuffer,
897 						  DWORD dwGfxPipelineSelect);
898 
899 	 GENOS_STATUS(*pfnSendVfeState) (PGENHW_HW_INTERFACE pHwInterface,
900 					 PGENOS_COMMAND_BUFFER pCmdBuffer,
901 					 BOOL blGpGpuWalkerMode);
902 
903 	 GENOS_STATUS(*pfnSendCurbeLoad) (PGENHW_HW_INTERFACE pHwInterface,
904 					  PGENOS_COMMAND_BUFFER pCmdBuffer);
905 
906 	 GENOS_STATUS(*pfnSendIDLoad) (PGENHW_HW_INTERFACE pHwInterface,
907 				       PGENOS_COMMAND_BUFFER pCmdBuffer);
908 
909 	 GENOS_STATUS(*pfnSendMediaObjectWalker) (PGENHW_HW_INTERFACE
910 						  pHwInterface,
911 						  PGENOS_COMMAND_BUFFER
912 						  pCmdBuffer,
913 						  PGENHW_WALKER_PARAMS
914 						  pWalkerParams);
915 
916 	 GENOS_STATUS(*pfnSendMISetPredicateCmd) (PGENHW_HW_INTERFACE
917 						  pHwInterface,
918 						  PGENOS_COMMAND_BUFFER
919 						  pCmdBuffer,
920 						  DWORD PredicateEnable);
921 
922 	 GENOS_STATUS(*pfnSendMIArbCheckCmd) (PGENHW_HW_INTERFACE pHwInterface,
923 					      PGENOS_COMMAND_BUFFER pCmdBuffer);
924 
925 	 GENOS_STATUS(*pfnSendGpGpuWalkerState) (PGENHW_HW_INTERFACE
926 						 pHwInterface,
927 						 PGENOS_COMMAND_BUFFER
928 						 pCmdBuffer,
929 						 PGENHW_GPGPU_WALKER_PARAMS
930 						 pGpGpuWalkerParams);
931 
932 	 GENOS_STATUS(*pfnSendBatchBufferStart) (PGENHW_HW_INTERFACE
933 						 pHwInterface,
934 						 PGENOS_COMMAND_BUFFER
935 						 pCmdBuffer,
936 						 PGENHW_BATCH_BUFFER
937 						 pBatchBuffer);
938 
939 	 GENOS_STATUS(*pfnSendBatchBufferEnd) (PGENHW_HW_INTERFACE pHwInterface,
940 					       PGENOS_COMMAND_BUFFER
941 					       pCmdBuffer);
942 
943 	 GENOS_STATUS(*pfnSendPipeControl) (PGENHW_HW_INTERFACE pHwInterface,
944 					    PGENOS_COMMAND_BUFFER pCmdBuffer,
945 					    PGENOS_RESOURCE pOsResource,
946 					    BOOL AllocEnable,
947 					    DWORD dwOffset,
948 					    INT ControlMode,
949 					    INT FlushMode, DWORD dwSyncWord);
950 
951 	 GENOS_STATUS(*pfnSendStoreDataImmCmd) (PGENHW_HW_INTERFACE
952 						pHwInterface,
953 						PGENOS_COMMAND_BUFFER
954 						pCmdBuffer,
955 						PGENHW_STORE_DATA_IMM_PARAM
956 						pParam);
957 
958 	 GENOS_STATUS(*pfnSendLoadRegImmCmd) (PGENHW_HW_INTERFACE pHwInterface,
959 					      PGENOS_COMMAND_BUFFER pCmdBuffer,
960 					      PGENHW_LOAD_REGISTER_IMM_PARAM
961 					      pParam);
962 
963 	 GENOS_STATUS(*pfnSendStateSip) (PGENHW_HW_INTERFACE pHwInterface,
964 					 PGENOS_COMMAND_BUFFER pCmdBuffer);
965 
966 	 GENOS_STATUS(*pfnSendDebugCtl) (PGENHW_HW_INTERFACE pHwInterface,
967 					 PGENOS_COMMAND_BUFFER pCmdBuffer);
968 
969 	 GENOS_STATUS(*pfnSetupBufferSurfaceState) (PGENHW_HW_INTERFACE
970 						    pHwInterface,
971 						    PGENHW_SURFACE pSurface,
972 						    PGENHW_SURFACE_STATE_PARAMS
973 						    pParams,
974 						    PGENHW_SURFACE_STATE_ENTRY *
975 						    ppSurfaceEntry);
976 
977 	 GENOS_STATUS(*pfnSendIndirectPatch) (PGENHW_HW_INTERFACE pHwInterface,
978 					      PGENOS_COMMAND_BUFFER pCmdBuffer,
979 					      PGENHW_INDIRECT_PATCH_PARAM
980 					      pParam);
981 
982 	 VOID(*pfnAddBatchBufferEndCmdBb) (PGENHW_HW_INTERFACE pHwInterface,
983 					   PGENHW_BATCH_BUFFER pBatchBuffer);
984 
985 	 VOID(*pfnSkipBatchBufferEndCmdBb) (PGENHW_HW_INTERFACE pHwInterface,
986 					    PGENHW_BATCH_BUFFER pBatchBuffer);
987 
988 	 VOID(*pfnAddMediaObjectCmdBb) (PGENHW_HW_INTERFACE pHwInterface,
989 					PGENHW_BATCH_BUFFER pBatchBuffer,
990 					PGENHW_HW_MEDIAOBJECT_PARAM pParam);
991 
992 	 VOID(*pfnAddPipeControlCmdBb) (PGENHW_HW_INTERFACE pHwInterface,
993 					PGENHW_BATCH_BUFFER pBatchBuffer,
994 					PGENHW_PIPECONTROL_PARAM pParam);
995 
996 	 VOID(*pfnSkipPipeControlCmdBb) (PGENHW_HW_INTERFACE pHwInterface,
997 					 PGENHW_BATCH_BUFFER pBatchBuffer,
998 					 PGENHW_PIPECONTROL_PARAM pParam);
999 
1000 	 GENOS_STATUS(*pfnAddPipelineFlushPatch) (PGENHW_HW_INTERFACE
1001 						  pHwInterface,
1002 						  PGENOS_COMMAND_BUFFER
1003 						  pCmdBuffer,
1004 						  PGENHW_BATCH_BUFFER
1005 						  pBatchBuffer);
1006 
1007 	 GENOS_STATUS(*pfnSkipPipelineFlushPatch) (PGENHW_HW_INTERFACE
1008 						   pHwInterface,
1009 						   PGENOS_COMMAND_BUFFER
1010 						   pCmdBuffer,
1011 						   PGENHW_BATCH_BUFFER
1012 						   pBatchBuffer);
1013 
1014 	 VOID(*pfnConvertToNanoSeconds) (PGENHW_HW_INTERFACE pHwInterface,
1015 					 UINT64 iTicks, PUINT64 piNs);
1016 
1017 	 DWORD(*pfnGetScratchSpaceSize) (PGENHW_HW_INTERFACE pHwInterface,
1018 					 DWORD iPerThreadScratchSpaceSize);
1019 
1020 	 BOOL(*pfnIs2PlaneNV12Needed) (PGENHW_HW_INTERFACE pHwInterface,
1021 				       PGENHW_SURFACE pSurface);
1022 
1023 } GENHW_HW_INTERFACE;
1024 
1025 #ifdef __cplusplus
1026 extern "C" {
1027 #endif
1028 
1029 GENOS_STATUS IntelGen_HwInitInterfaceOS(PGENHW_HW_INTERFACE pHwInterface,
1030 				      PGENOS_INTERFACE pOsInterface);
1031 
1032 DWORD IntelGen_HwGetCurBindingTableBase(PGENHW_SSH pSSH);
1033 
1034 DWORD IntelGen_HwGetCurSurfaceStateBase(PGENHW_SSH pSSH);
1035 
1036 VOID IntelGen_GetPixelsPerSample(GENOS_FORMAT format,
1037 				 PDWORD pdwPixelsPerSampleUV);
1038 
1039 #ifdef __cplusplus
1040 }
1041 #endif
1042 
1043 #endif
1044